Digital CMOS Process Research Articles

High-speed replicating current comparators for analog convolutional decoders

This paper describes two high-speed replicating current comparators (RCCs) for use in convolutional decoders. One RCC operates asynchronously by means of a negative feedback mechanism that provides an accurate virtual ground for input current summation and comparison. This circuit requires realization in BiCMOS technology. The other RCC is synchronous and can be implemented using a digital CMOS process. Since this RCC requires positive feedback, resetting is required after each operating cycle. In addition to replicating the winner, both types of RCCs identify the winning input by means of a digital binary output voltage. The RCCs were fabricated in a 0.8 /spl mu/m BiCMOS process and feature a maximum input signal range in excess of 200 /spl mu/A. The asynchronous RCC operates at speeds up to about 200 MHz, has a resolution of 2 /spl mu/A, and consumes 5.8 mW from a 2.8 V power supply. The synchronous RCC operates up to about 100 MHz, has a resolution of 1.2 /spl mu/A, and consumes 2.5 mW from a 3 V power supply. The measurements are compared with post-layout simulations.

Two-stage high swing fully integrated tunable quadrature sine oscillator

A new fully integrated two-stage operational transconductance amplifier-capacitor (OTA-C) sine oscillator circuit configuration using a 0.5 μm CMOS digital process is described. A simple linear impedance analysis is presented to predict the amplitude and distortion of oscillation. The accuracy of this approach is examined by comparing calculated, simulated and measured results. Transconductance tuning keeps the startup condition satisfied within the frequency range from 2 to 11 MHz.

A 2.7-V elliptical MOSFET-only g/sub m/C-OTA filter

The g/sub m/C-operational transconductance amplifier (OTA) technique relaxes transconductor output swing and dc-gain requirements, which makes it a suitable candidate for low-voltage circuits. To reduce the power consumption of OTA's, an excess phase shift compensation with an automatic tuning circuit is used. A floating triode-region transconductor with a novel biasing to compensate the effect of channel-length modulation is presented. The two independent common-mode levels in a g/sub m/C-OTA integrator are utilized to bias a pMOS as a linear capacitor. This enables the realization of the floating-transmission zero capacitors with a pure digital CMOS process. The implementation and the experimental results for a third order 2.7-V all-MOS elliptical filter with 64-dB dynamic range and 0.1% linearity are presented.

A multibit ΣΔ modulator in floating-body SOS/SOI CMOS for extreme radiation environments

This paper presents the design of an experimental first-order /spl Sigma//spl Delta/ modulator with 4-bit internal quantization, fabricated in a 1.5-/spl mu/m space-qualified radiation-hard partially depleted silicon-on-sapphire (SOS) digital CMOS process. This converter architecture has been chosen partly to allow investigation into the design of a range of common analog functions with two key issues in mind: one of technology and one environmental. First, both the architecture and the circuit design are optimized using a variety of unconventional techniques to account for the influence of extreme bias-dependent, radiation-induced threshold-voltage shifts of up to 1 V, as well as poor 1/f device noise. Second, the circuitry is specially adapted to accommodate the floating-body behavior of this type of process, wherein drain conductance varies considerably with drain bias and frequency. The design techniques are directly applicable to very large-scale-integration silicon-on-insulator (SOI) design, where similar device physics are encountered. Notwithstanding the severe constraints on the design, the fabricated circuit provides 9.7 bits of dynamic range in a 63-kHz signal bandwidth, only degrading to 9.1 bits after 23 Mrad(Si) of total dose /spl gamma/ radiation.

A 3-V GSM baseband transmitter

A dual-channel baseband transmitter has been designed for global system for mobile communications (GSM) cellular phone application. It has been fabricated in a 0.35-/spl mu/m digital CMOS process as part of a single-chip solution for baseband processing. Each channel consists of a switched-capacitor digital-to-analog converter, a switched-capacitor filter, a class-AB buffer, and an active-RC filter. The lack of on-chip precision capacitors and resistors poses a major challenge in designing these analog building blocks. Another key implementation issue is to maintain the performance of these analog circuits in the presence of substantial substrate noise from the digital signal-processing core. The current consumption is 8.8 mA, and the total active area is 5.1 mm/sup 2/. The channel response meets the Gaussian minimum-shift-keying spectral mask.

A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driver for Ethernet and fast Ethernet networking applications

A fast line driver has been developed for networking applications in a 0.4-/spl mu/ digital CMOS process. It is intended to drive cables with large, low-distortion sinewaves for 10BASE-T and sharp-edged pulses for 100BASE-T-type data communications. The driver has a fully differential architecture and uses a current-feedback approach to achieve small- as well as large-signal closed-loop bandwidths in excess of 100 MHz. It can drive a 10-MHz, 5-V/sub pp/ sinewave across a 50-/spl Omega/ load from a 3.3-V power supply with a total harmonic distortion of -43 dB. The quiescent power consumption of the driver is 25 mW, while its area is 0.15 mm/sup 2/.

Efficient SI wave elliptic filters based on direct and inverse Bruton transformations

The paper describes an efficient method for designing switched-current elliptic-wave filters. The method is based on applying direct or inverse Bruton circuit transformation to an LC reference prototype prior to obtaining the equivalent wave filter. The method provides significant reduction in the switched-current circuit complexity, particularly for high-order filters, when compared with previously published results. This is achieved by applying a suitable Bruton transformation to an appropriate prototype which results in simplified and reduced number of wave adapters. Simulation results based on 1.2 /spl mu/m CMOS digital process for highpass and bandpass elliptic filters are also included.

Balanced compensation for highly linear MOSFET gate capacitor branch

The compatibility of the switched-capacitor technique with standard digital CMOS processes utilising MOSFET gate capacitance has recently been investigated. Owing to its high voltage-dependence, a technique for enhancing linearity which is suitable for non-delay-free circuits is proposed. The technique was verified by simulation to demonstrate its effectiveness for linearity improvement.

Very Low-Voltage Switched-Current Circuits in Standard Digital CMOS Process

The inherent simplicity of switched-current circuits makes them suitable for low-voltage and very low voltage operation. This paper presents the design of 1.2-V switched-current circuits in a standard digital CMOS process. The core elements are the proposed fully differential SI memory cell and high resolution current quantizer. A delay line and a second-order delta-sigma modulator are implemented and measured. The delay line occupies an active chip area of 0.2 mm^2 and dissipates a power of 0.2 mW, and the modulator occupies an active chip area of 0.47 mm^2 and dissipates a power of 0.78 mW. The measured total harmonic distortion of the delay line is less than −48 dB with a 60% input modulation index and the measured dynamic range of the modulator is 10 bits.

A QCIF Resolution Binary I/O CNN-UM Chip

In this paper is reported a Cellular Nonlinear Network Universal Machine realization where there are 176 × 144 active cells. The size of the network is the standardized QCIF video image format and the design is aimed to be used in segmenting video images in future video applications requiring very low bit-rate for image transmission. The achieved cell density is 3000 cells/mm^2 with a 0.25 micron standard digital CMOS process. Different building blocks inside the cell are given in detail and also the other implemented circuitry is thoroughly discussed. The physical realization of the design is also reported.

A -90-dB THD rail-to-rail input opamp using a new local charge pump in CMOS

This paper describes the principle and design of a CMOS rail-to-rail input operational amplifier with THD performance of -90 dB which is suited for high-quality audio systems. A new output stage has been used featuring an output suing that extends to either supply rail and is capable of driving a low ohmic load (32 /spl Omega/). The opamp, which is realized in a 0.5-/spl mu/m 3.3-V digital CMOS process, uses a standard two-stage Miller configuration. The rail-to-rail input functionality is achieved with a new area-efficient on-chip charge pump which provides the local supply voltage for the input differential pair. THD levels below -90 dB have not yet been shown with existing rail-to-rail techniques. This rail-to-rail input configuration also behaves independently of the common mode level with respect to transconductance and slewing characteristics.

High-accuracy charge-redistribution SC video bandpass filter in standard CMOS

A differential switched-capacitor recursive bandpass filter is presented based on a charge-redistribution technique. The center frequency is 4.286 MHz with a quality factor of 16, and the sampling frequency is 25.7 MHz. It is specifically intended for the high-frequency deemphasis of SECAM TV video signals. The active capacitors are realized using only a sandwich construction of poly-metal1-metal2. A dual-input single-stage telescopic OTA is proposed, which has a very high current efficiency. The filter behavior is very linear, and achieves a dynamic range of 79 dB for 1% third-order intermodulation. The power consumption is only 4 mW for a 5-V supply voltage, and is realized in 0.75 mm/sup 2/ in a standard 0.8-/spl mu/m double-metal digital CMOS process.

Low-voltage class AB buffers with quiescent current control

This paper presents a simple class AB buffer which is suitable for low-voltage (1.5 V) applications. The proposed buffer uses an adaptive load to reduce the sensitivity of the quiescent current to the process variation. The main feature of this scheme is its simplicity. The circuit was fabricated in a 2.0 /spl mu/m digital CMOS process. Experimental results demonstrate that the buffer can operate with a supply voltage below 2 V, and it has the capability to drive small resistive loads.

Design techniques for 1.5-V low-power CMOS current-mode cyclic analog-to-digital converters

Design techniques to realize low-voltage low-power (LVLP) cyclic current-mode analog-to-digital converters (IADCs) in the CMOS digital process are presented. First, a modified reference-nonrestoring (MRN) algorithm is proposed. By using the MRN algorithm, the digital correction (DCN) technique ran be embedded into the cyclic architecture to reduce the linearity errors caused by the comparator inaccuracy and the offset of the sample/hold (S/H) operations. Moreover, new LVLP fully differential current-mode circuits performing the S/H, multiplication-by-2, and current comparison are also developed to implement the cyclic IADC without the use of linear capacitors or a multithreshold process. An experimental chip for the proposed IADC with an active area of 4 mm/sup 2/ has been fabricated in 0.8 /spl mu/m n-well CMOS technology. With a 1.5 V supply voltage, the fabricated IADC achieves 10 bit resolution with the differential nonlinearity (DNL) of 0.63 LSB and integral nonlinearity (INL) of 1.4 LSB when operated at a 12 ks/s conversion rate. The power consumption of the IADC core circuit is 2 mW.

Oversampling current sample/hold structures for digital CMOS process implementation

The inaccuracies obtained by sampling a dynamic input signal is a major source of error in current-mode circuits. A sampled-data feedback architecture is presented for the design of a high-linearity current sample/hold that uses oversampling to overcome the nonlinearity of internal components. Both system and circuit level considerations are discussed, culminating in the design and implementation of both first- and second-order structures in a 2 /spl mu/m p-well CMOS process. Limited test results show a linearity of up to 69 dB at a sampling rate of 5 MHz. These circuits provide an excellent sampling stage for the realization of a high-resolution current-mode /spl Delta//spl Sigma/ A/D converter in a digital CMOS process.

Design techniques for a low-power low-cost CMOS A/D converter

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems. A switched-bias power-reduction technique reduces the total system power by 10%. A layout technique employing extra thin poly-layer lines instead of conventional dummy devices reduces plasma-induced comparator offsets. Based on a standard digital CMOS process with a single poly layer, the ADC adopts metal-to-metal capacitors for internal charge storage. The experimental ADC was fabricated in a 0.6 /spl mu/m single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply voltage. The measured differential and integral nonlinearities of the prototype are less than /spl plusmn/0.8 and /spl plusmn/1.8 LSB, respectively.

Switched-voltage: An adaptation of switched-currents for voltage-mode design

A novel sampled-data signal processing technique is proposed, termed switched-voltage (SV). The technique is a dual approach to the recent switched-current technique. As with switched-current, the switched-voltage technique overcomes the incompatibility of the classical switched-capacitor technique to standard digital CMOS processes. The technique also relaxes the need for linear voltage-to-current and current-to-voltage converters in switched-currents for interfacing to the application environment.

A novel delay-locked loop based CMOS clock multiplier

On-chip clock-rate multiplication is usually achieved using a phase-locked-loop (PLL) circuit. However, integration of such an analog-intensive and noise-sensitive circuit with a digital circuit constitutes a major challenge. As an alternative solution, this paper proposes an attractive fully integratable delay-locked loop (DLL) based clock-rate multiplier by a modest integer factor. The implementation of the total circuit in the standard digital CMOS process is extremely simple and robust. The circuit can be part of a standard digital cell library and can easily be integrated with digital circuits. Simulation and experimental results are provided to evaluate the performance of the proposed circuit.

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm/sup 2/

A 10-b current steering CMOS digital-to-analog converter (DAC) is described, with optimized performance for frequency domain applications. For sampling frequencies up to 200 MSample/s, the spurious free dynamic range (SFDR) is better than 60 dB for signals from DC to Nyquist. For sampling frequencies up to 400 MSample/s, the SFDR is better than 55 dB for signals from DC to Nyquist. The measured differential nonlinearity and integral nonlinearity are 0.1 least significant bit (LSB) and 0.2 LSB, respectively. The circuit is fabricated in a 0.35-/spl mu/m, single-poly, four-metal, 3.3 V, standard digital CMOS process and occupies 0.6 mm/sup 2/. When operating at 500 MSample/s, it dissipates 125 mW from a 3.3 V power supply. This DAC is optimized for embedded applications with large amounts of digital circuitry.

Low-voltage, 10 bit switched-current ADC with 20 MHz input bandwidth

Fully-differential first-generation switched-current memory cells with common-mode feedforward were used to implement a 1.5 bit/stage pipelined A/D converter in a standard digital CMOS process. The peak effective number of bits (ENOB) for input frequencies over 1 MHz is 7.43, and with a 20 MHz input signal sampled at 3 M sample/s, the measured SFDR and SNDR are 45.1 and 40.8 dB, respectively.