Digital Circuit Applications Research Articles

Comparison and performance optimization of two absolute circuit designs based on Multisim

Digital circuits are crucial in today's technology, underpinning infrastructure such as computing, communicating, and intelligent devices. Its high efficiency, accuracy and programmable capability drive the development of information processing, data transmission and automation systems. The application of digital circuits has promoted innovation in artificial intelligence, the Internet of Things and other fields, providing strong support for the intelligence and interconnection of modern society. The absolute value circuit is discussed in this paper. The absolute value circuit is implemented for converting the negative value of the input signal to a positive value, ensuring that the output signal is always non-negative. Its significance is to handle application scenarios that require non-negative values, such as signal processing, audio amplification, and sensor output. Through the absolute value circuit, negative value can avoid the negative effect on the subsequent circuit, and improve the stability and accuracy of the system. This paper first introduces all the gates used in the circuit, points out the functions of each gate circuit, and then puts forward two absolute value circuit designs, explaining their working principles, differences and advantages and disadvantages. Then the minimum delay is analyzed by the critical path logic and the sizes of each logic gate is given. Then the supply voltage is optimized after selecting the design with the smallest delay to reduce energy consumption.

Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET

In this investigation, a suppressed channel-rectangular core–shell double gate junctionless field effect transistor (SC_RCS_DGJLFET) is simulated to enhance the junctionless device’s performance. This study leverages a core–shell architecture and channel suppression technique to improve the gate controllability over the channel region which helps in substantial depletion of the shells in the OFF state of the device. When compared to conventional double gate JLFETs (C_DGJLFET) and rectangular core–shell double gate JLFETs (RCS_DGJLFET), the performance of the SC_RCS_DGJLFET is superior in terms of IOFF, ION/IOFF ratio, DIBL and subthreshold slope (SS). The SC_RCS_DGJLFET achieves an ultra-low IOFF of 7.033 × 10−16 A, indicating a low leakage current with an impressive ION/IOFF = 5.092 × 1011 . Other performance parameters such as subthreshold slope and DIBL has also been improved for the SC_RCS_DGJLFET device. Subthreshold slope has been decresesd by 4.76% whereas the DIBL decreased by 33.82% when compared to existing RCS_DGJLFET. Additionally, to analyze the effect of doping on the device performance, the core doping in SC_RCS_DGJLFET is varied for fixed shell doping. The study found that fixing core doping to an appropriate value is a crucial parameter to achieve good device performance. The impact of variation of oxide extension towards the source and drain LextS/LextD in SC_RCS_DGJLFET is also studied for the first time in the core–shell architecture which has further improved the device’s performance. Finally, a CMOS inverter is designed using the proposed device that provides valuable insights into its suitability for digital circuit applications and verifies its performance benefits compared to existing transistor technologies. The SC_RCS_DGJLFET based CMOS inverter shows a sharp transition in voltage transfer characteristics (VTC), indicating fast switching speed and precise signal processing capabilities when compared to a CMOS inverter based on a conventional double gate junctionless field effect transistor (C_DGJLFET). Moreover, the transient characteristics of the SC_RCS_DGJLFET based CMOS inverter exhibit an improved output voltage swing, suggesting enhanced dynamic behaviour and stability during logic state transitions.

Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain β values >1100, ft>500 GHz, fmax>1300 GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of ∼1.3 ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the β value for WED-based devices when subjected to temperatures exceeding 340 K. In contrast, BED-based devices demonstrate a comparatively smaller variation in β at temperatures above 340 K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

Principles of Logic Design with Nanoscale Thin Film Memristive Systems for High Performance Digital Circuit Applications

The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

A Method to Probe the Interfaces in La2−xSrxCuO4-LaSrAlO4-La2−xSrxCuO4 Trilayer Junctions

C-axis trilayer cuprate Josephson junctions are essential for basic science and digital circuit applications of high-temperature superconductors. We present a method for probing the interface perfection in La2−xSrxCuO4 (LSCO)-LaSrAlO4 (LSAO)-La2−xSrxCuO4 trilayer junctions. A series of LSCO-LSAO superlattices with atomically smooth surfaces and sharp interfaces were grown by the atomic-layer-by-layer molecular beam epitaxy (ALL-MBE) technique. We have systematically varied the thickness of LSCO and LSAO layers with monolayer precision. By studying the mutual inductance and electrical transport in these superlattices, we detect the non-superconducting (“dead”) layers at the interfaces and quantify their thicknesses. Our results indicate that two optimally doped LSCO monolayers just above and below the one monolayer LSAO barrier are no longer superconducting, rendering the actual barrier thickness of five monolayers. Next, we have shown that introducing a protective highly-overdoped LSCO layer reduces the thickness of dead layers by one or two monolayers.

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation.

The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si0.7Ge0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Study on high temperature storage reliability of crystal Oscillator

As the most accurate and stable oscillator, the crystal oscillator can provide a stable frequency signal source for the circuit. It has an extremely wide range of applications in various digital circuits and precision instruments, and is an important type of frequency control device. In the field of military and aerospace, crystal oscillators not only require good frequency accuracy and stability under long-term working conditions, but also require high storage reliability, which can meet the storage life requirements of products. In this paper, a high-temperature storage reliability study was conducted for a certain model of crystal oscillator. The high-temperature storage reliability test was designed and carried out. Through the degradation analysis and failure analysis of the test samples, the degradation trend of this model of crystal oscillator under high-temperature storage conditions and the failure mechanism of the leakage failure caused by the galvanic corrosion at the internal solder joints were found. The study in this paper has certain reference significance for the reliability research of crystal oscillator.

A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications

In this paper, the workability of a Negative Capacitance (NC)-Double Gate (DG) Tunnel FET (NC-DGTFET) for digital logic circuit implementation has been detailed. New analytical modelling of the drain current of the NC-DGTEFT considering the band to band tunneling (BTBT), Band tail tunneling (BTT) and Source drain tunneling (SDT) have been investigated. Significant IOÑ0.025 μA/μm at 250 mV and SS∼12mv/dec - 22mv/dec with very low IOFF (∼fA/μm) is observed with the optimized device. SILVACO ATLAS and MATLAB have been used to validate the proposed model. The modeled NC-DGTFET based Inverter, NAND/NOR has been implemented and the power, delay propagation, and the power delay product (PDP) of the circuit have been analyzed to show the energy efficacy of the NC-DGTFET in the sub-threshold regime (STR) with respect to baseline TFET (B-TFET). To evaluate the impact of the Miller's effects on the digital performances, NC-DGTFET-based five stages Inverter with Fanout = 1 is considered a device under test (DUT) here. Peak overshoot voltage and delay for different fanout and ferroelectric thickness are detailed to show the efficacy of the proposed logic circuits in sub-threshold regime. Both the cross talk and the Miller effects are mitigated significantly in the NC-DGTFET-based digital circuits.

Modified priority encoder based hardware efficient N-bit comparator

ABSTRACT Digital Circuits applications are expanding rapidly in modern times because they generate correct signals without errors or interferences. These digital circuits play important roles in data storage operation, as well as the implementation of image processing applications on hardware where the power, speed, and area of an electronic device play a significant role, particularly in the field of modern VLSI technology. The digital comparator with more number of bits plays an important role in image processing applications. In the proposed research paper, an attempt is made to design a speed and area efficient 32-bit comparator. To improve the speed of the comparator a modified priority encoder technique is used. It shows that the area of proposed 32-bit digital comparator consumes 573.73 units which are 20% better than when compared with the conventional comparators and the speed improved by 50% when compared with the Conventional Comparators. The proposed implementation is simulated on the ‘Encounter(R) RTL Compiler RC14.28’.

Progress toward picosecond on-chip magnetic memory

We offer a perspective on the prospects of ultrafast spintronics and opto-magnetism as a pathway to high-performance, energy-efficient, and non-volatile embedded memory in digital integrated circuit applications. Conventional spintronic devices, such as spin-transfer-torque magnetic-resistive random-access memory (STT-MRAM) and spin–orbit torque MRAM, are promising due to their non-volatility, energy-efficiency, and high endurance. STT-MRAMs are now entering into the commercial market; however, they are limited in write speed to the nanosecond timescale. Improvement in the write speed of spintronic devices can significantly increase their usefulness as viable alternatives to the existing CMOS-based devices. In this article, we discuss recent studies that advance the field of ultrafast spintronics and opto-magnetism. An optimized ferromagnet–ferrimagnet exchange-coupled magnetic stack, which can serve as the free layer of a magnetic tunnel junction (MTJ), can be optically switched in as fast as ∼3 ps. Integration of ultrafast magnetic switching of a similar stack into an MTJ device has enabled electrical readout of the switched state using a relatively larger tunneling magnetoresistance ratio. Purely electronic ultrafast spin–orbit torque induced switching of a ferromagnet has been demonstrated using ∼6 ps long charge current pulses. We conclude our Perspective by discussing some of the challenges that remain to be addressed to accelerate ultrafast spintronics technologies toward practical implementation in high-performance digital information processing systems.

General Modeling Method of Threshold-Type Multivalued Memristor and Its Application in Digital Logic Circuits

This paper presents a general modeling method for threshold-type multivalued memristors. Through this memristor modeling method, it is very simple to establish threshold-type memristor behavior models with different numbers of memristance elements, and these models are verified by numerical MATLAB simulations. A corresponding circuit-level SPICE model of the ternary memristor behavior model is developed and simulated in LTspice, shown to be consistent with the MATLAB results. Finally, the SPICE model is used to design the AND gate, OR gate, and three NOT gates of ternary state-based logic, and the effectiveness of the circuit is proved by LTSpice simulation.

A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs

The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device’s response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm channel length have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

Comparative Performance and Reliability Analysis of Doping and Junction Free Devices with High-κ/Vacuum Gate Dielectric

A comparative evaluation of channel hot carrier (CHC) reliability and pursuance of dopingless FET (DL JLFET) and junctionless FET (JLFET) are studied for various dielectrics and compared with conventional dielectric (SiO2) JLFET. The use of dielectrics such as vacuum near the drain and the high-κ (HfO2) near the source in DL JLFET (VacuHDL JLFET) allows better pursuance and reliability against channel hot carrier (CHC) effects. A simulation study has shown that the pursuance of VacuHDL in terms of Ion/Ioff ratio is improved by 4.5, 19.38 and 39.58 times, respectively, in comparison with vacuum based DL, HJL and JL. Similarly, the intrinsic delay of VacuHDL is improved by 9.5%, 56.8% and 58.7%, respectively, in comparison with VacuDL, VacuHJL and VacuJL. Hence, VacuHDL is a potential candidate for digital circuit applications. Further, we have found that vacuum-based HDL and HJL are more immunes against CHC stress and shown that the drain current of vacuHDL and vacuHJL is reduced by 6.9% and 17.5%, respectively, in comparison with conventional dialectic (SiO2) based DL and JL which is 10.4% and 20.5%. Hence, the incorporation of vacuum dielectric towards drain terminal is helpful in reducing CHC induced effect in comparison with conventional dielectric.

Optimization of Gate all-around Junctionless Transistor Using Response Surface Methodology

In this paper, a response surface methodology (RSM) –custom design based multiobjective optimization approach is proposed to optimize the electrical behaviour of n-type and p-type gate all around junctionless transistor (GAA JLT). The proposed approach combines the universal optimization and fitting capability, providing reliable and cost-effective optimized designs suitable for analog and digital circuit applications. A compact analytical expression is obtained for the electrical parameters of the device. The developed expression is used to construct multi-objective functions required for optimization. The proposed method provides optimal electrical and dimensional parameters of the device to obtain better performance with reduced simulation time. The optimized design has been incorporated in the CMOS inverter circuit and its performance is also analyzed.

Cylindrical SOI Schottky Barrier MOSFET with High Linearity and Low Static Power for Digital and Analog Circuits Application

Non-linearity and static power consumption are major challenges in the designing of digital and analog circuits. To improve the performance of digital and analog circuits, a proper selection of MOSFET device architecture is essential. The MOSFET device architecture with low static power dissipation and high linearity results in improves overall performance at the circuit level. In this work, a detailed analysis of cylindrical Silicon-on-Insulator (SOI) Schottky Barrier (SB) MOSFET is done for analog and digital circuit applications. The analog device parameters and device non-linearity parameters for SOI SB MOSFET are extracted and compared with SB MOSFET and Dielectric Pocket (DP) SB MOSFET. The SOI SB MOSFET shows an improvement of 6.905% in output conductance (gds), 130.513% in early voltage (Vea), 240.74% in transconductance generation factor (TGF), 35.901% in transconductance frequency product (TFP), 23.529% in the gain-bandwidth product (GBWP), 25.542% in voltage gain (Av), 130.968% in gain frequency product (GFP), and 179.964% in gain transconductance frequency product (GTFP). Third-order extrapolated voltage (VIP3), third-order extrapolated power (IIP3), and extrapolated intermodulation power (IMD3) have also improved in comparison to SB MOSFET. The Atlas 3-D device simulation tool is used for numerical simulations.

Integrator based on current-controlled magnetic domain wall

Integrators are widely used in industrial controls, signal processing, and computing. However, traditional resistor–capacitor integrators incur leakage errors and zero drift, hindering their accuracy. By contrast, spintronic devices with good scalability and endurance for memory and logic applications in digital circuits have yet to be studied for analog circuit elements. Here, we propose a single-device spintronic integrator based on the current-controlled magnetic domain wall (DW). Continuous DW motion and correlated changes in the anomalous Hall resistance (or magneto-resistance) are encoded as an analog output signal, which is modulated by an input current through the spin–orbit-torque effect. Waveform transformation and phase-shift functions are demonstrated using Hall-bar devices. The spintronic integrator could pave the way for the spin-based analog computing with high reliability, high endurance, and good compatibility with the CMOS process.

Advances for Enhanced GaN-Based HEMT Devices with p-GaN Gate

With the development of high-voltage switches and high-speed RF circuits, the enhancement mode(E-mode) AlGaN/GaN HEMTs have become a hot topic in those fields. The E-mode GaN-based HEMTs have channel current at the positive gate voltage, greatly expanding the device in low power digital circuit applications. The main methods to realize E-mode AlGaN/GaN HEMT power devices are p-GaN gate technology, recessed gate structure, fluoride ion implantation technology and Cascode structure (Cascode). In this paper, the advantage and main realizable methods of E-mode AlGaN/GaN HEMT are briefly described. The research status and problems of E-mode AlGaN/GaN HEMT devices fabricated by p-GaN gate technology are summarized. The advances of p-GaN gate technology, and focuses on how these research results can improve the power characteristics and reliability of E-mode AlGaN/GaN HEMT by optimizing device structure and improving process technology, are discussed.

Performance Investigation of Organic Thin Film Transistor on Varying Thickness of Semiconductor Material: An Experimentally Verified Simulation Study

Physics-based two-dimensional numerical simulations are performed to analyze the device characteristics of tri-isopropylsilylethynyl (TIPS)-pentacene organic thin-film transistor (OTFT) fabricated using drop-casting technique. Further, using simulation technique enabling calibration this paper also presents the systematic study of the impact of active layer (TIPS-pentacene) thickness on device characteristics. The extracted parameters such as electric field intensity, current density, current On/Off ratio, and mobility exhibit variation with scaling down in active layer thickness from 500 to 100 nm. The study also revealed that Off current and On/Off current ratio (IOn/IOff) is highly dependent on the thickness of the semiconductor layer. Furthermore, the highest value of IOn/IOff is obtained at 100-nm thickness of TIPS-pentacene, which can be used for various fast-switching applications in digital circuits. Simulated results are not only reasonably matching with experimental results but also provide insight on charge transportation at the semiconductor-dielectric interface and in the bulk of TIPS-pentacene layer.

A systematic review on full adder designs in Quantum-dot Cellular Automata

Abstract Quantum-dot Cellular Automata (QCA) is a promising transistor-less nanotechnology that is used for designing digital circuits at nano dimensions. Its major advantage is that QCA enables the circuits to operate at faster rates compared to CMOS. Any large digital circuit application uses full adder as a basic component. Many researchers have designed full adders with different number of quantum cells, in various sizes and layers and different delays. This paper presents a detailed report of all existing full adders designed using QCA. A comparison of full adder designs is carried out to identify the better one. Simulation and analysis of existing QCA designed full adders is performed using QCADesigner tool.

Diffusion-activated high performance ZnSnO/Yb2O3 thin film transistors and application in low-voltage-operated logic circuits

The flourishing metal-oxide high-k dielectric materials have been regarded as the vital components of low voltage operated flexible transparent electronic devices. We herein report that ytterbium oxide (Yb2O3) and ZnSnO (ZTO) thin films were firstly integrated into ZTO-based thin film transistors (TFTs) with superior performance. Results have indicated that the 500 ℃-annealed ZTO/Yb2O3 TFTs possess the large saturation mobility of 9.1 cm2 V−1 S−1 and the high on/off current ratio of 2.15 × 107, which even surpass those of reported In-based TFTs. The deteriorative electrical properties in the aging process can be attributed to the carrier capture mechanism. However, the 460 ℃-processed TFTs demonstrate a tenfold increase in saturated mobility and an increase in on/off current ratio after 10 days aging. The inspiring electrical properties are attributed to the diffusion-activated carrier enhancement mechanism and electrons donor role of water molecular, which introduces a facile method to boost the device performance at lower processing temperatures. The neglected threshold voltage variations of 0.06 V and −0.2 V have been detected after bias stability experiments. The superior bias stability can be attributed to the charge delay effect induced by the continuous electric field. Meanwhile, the ultrahigh on/off current ratio of 1.1 × 107 and the recoverable transferring performance have verified the aging-activated mechanism. To confirm its potential application in digital circuits, a resistor-loaded inverter with gain of 5.6 has been constructed and good dynamic response behavior have been detected at a low voltage of 2 V. As a result, it can be concluded that the high temperature annealing TFTs need immediate encapsulation, while the performance of the lower temperature processing samples can be optimized after aging treatment, indicating the potential prospect in low power consumption large-scale flexible transparent devices.