Abstract
In this paper, a response surface methodology (RSM) –custom design based multiobjective optimization approach is proposed to optimize the electrical behaviour of n-type and p-type gate all around junctionless transistor (GAA JLT). The proposed approach combines the universal optimization and fitting capability, providing reliable and cost-effective optimized designs suitable for analog and digital circuit applications. A compact analytical expression is obtained for the electrical parameters of the device. The developed expression is used to construct multi-objective functions required for optimization. The proposed method provides optimal electrical and dimensional parameters of the device to obtain better performance with reduced simulation time. The optimized design has been incorporated in the CMOS inverter circuit and its performance is also analyzed.
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