Digital Chip Research Articles

Research on an Improved Three-Level SVPWM Modulation Algorithm Based on ID-NPC Topology

The conventional three-level SVPWM (Space Vector Pulse Width Modulation) algorithm is a basic modulation algorithm, which can be performed easily due to clear modulation ideas. Considering different criteria for sectors, however, the basic vector action time is calculated repeatedly, the selection of vector action sequence is cumbersome, and the algorithm execution time is extended as a result of processing by the digital processing chip. In order to better adapt to the PMSM (Permanent Magnet Synchronous Motor) control requirements of the ID-NPC (Improved Diodes Neutral Point Clamped) topology for converter control objects, the sector judgment part, time effect part and vector synthesis part are optimized according to the principles of saving hardware resources and shortening the execution cycle. The vector synthesis optimization algorithm of 2 × amplitude substitution and the vector synthesis algorithm of 1/2 × amplitude substitution are both proposed. Finally, the ID-NPC topology is used to verify the proposed modulation algorithm.

Design method for the high optical efficiency and uniformity illumination system of the projector.

How to balance the optical efficiency, illumination uniformity and the size of the illumination system is a challenging task in projector design. In this paper, we present a mathematical model describing the relationship between optical energy of the illumination system and the optical parameters and an optimization design method considering the light intensity distribution of the light source. By using the proposed method, two illumination systems are designed with different types of the digital micromirror device chips. In addition, we also propose a non-coaxial system to solve the deformation problem caused by the large flip angle of the DMD chip and further improve the illumination uniformity based on Scheimpflug principle. The optical efficiency and illumination uniformity of the illumination systems were verified and analyzed. The results indicate that the systems designed by the proposed method can provide a good design scheme and obtain a satisfactory utilization rate of the optical energy and higher uniformity.

Finding and Eliminating Noise and Interference in a Test Stand for Josephson Digital Chips

Sources of noise and interference in a test stand for Josephson digital integrated circuits have been identified and eliminated using a novel measurement technique. The digital output of the chip was fed into a spectrum analyzer while the output pattern was 1010. The DC bias was set at the boundary between correct and incorrect operation, a 50% bit error rate. Small AC noise currents on the bias made large changes in the bit error rate. This converted noise currents to amplitude modulation sidebands of the data pattern at half of the logic clock frequency, which was 625 MHz. AC currents were injected at 454 Hz to produce AM sidebands at 625 MHz ± 454 Hz. The sideband power was directly proportional to calibration tone power over the range 50 nA to 10 μA. Noise currents on the DC bias as small as 100 nA were clearly identified at 120 Hz. The largest noise currents in the test setup were found near 40 MHz. Their spectrum of evenly spaced tones indicated that the source was a switching power supply. When an idle relay controller was turned off, the noise tones immediately disappeared from the spectrum analyzer display, confirming the source of interference. This new and easy to use technique exploited bit error rate modulation to up convert AC noise currents from low frequencies to the range 625-675 MHz. The location of the noise currents was unambiguous, since only a 60 Hz noise current on the chip could produce an AM sideband at 625 MHz plus 60 Hz.

Sensitive, Rapid, and Automated Detection of DNA Methylation Based on Digital Microfluidics.

Biomarkers based on DNA methylation have attracted wide attention in biomedical research due to their potential clinical value. Therefore, a sensitive and accurate method for DNA methylation detection is highly desirable for the discovery and diagnostics of human diseases, especially cancers. Here, an integrated, low-cost, and portable point-of-care (POC) device is presented to analyze DNA methylation, which integrates the process of pyrosequencing in a digital microfluidic chip. Without additional equipment and complicated operation, droplets are manipulated by patterned electrodes with individually programmed control. The system exhibited an excellent sensitivity with a limit of detection (LOD) of 10 pg and a comparable checkout down to 5% methylation level within 30 min, which offered a potential substitute for the detection of DNA methylation. With the advantages of portability, ease of use, high accuracy, and low cost, the POC platform shows great potential for the analysis of tumor-specific circulating DNA.

Generation and Dynamics of Janus Droplets in Shear-Thinning Fluid Flow in a Double Y-Type Microchannel.

Droplets composed of two different materials, or Janus droplets, have diverse applications, including microfluidic digital laboratory systems, DNA chips, and self-assembly systems. A three-dimensional computational study of Janus droplet formation in a double Y-type microfluidic device filled with a shear-thinning fluid is performed by using the multiphaseInterDyMFoam solver of the OpenFOAM, based on a finite-volume method. The bi-phase volume-of-fluid method is adopted to track the interface with an adaptive dynamic mesh refinement for moving interfaces. The formation of Janus droplets in the shear-thinning fluid is characterized in five different states of tubbing, jetting, intermediate, dripping and unstable dripping in a multiphase microsystem under various flow conditions. The formation mechanism of Janus droplets is understood by analyzing the influencing factors, including the flow rates of the continuous phase and of the dispersed phase, surface tension, and non-Newtonian rheological parameters. Studies have found that the formation of the Janus droplets and their sizes are related to the flow rate at the inlet under low capillary numbers. The rheological parameters of shear-thinning fluid have a significant impact on the size of Janus droplets and their formation mechanism. As the apparent viscosity increases, the frequency of Janus droplet formation increases, while the droplet volume decreases. Compared with Newtonian fluid, the Janus droplet is more readily generated in shear-thinning fluid due to the interlay of diminishing viscous force, surface tension, and pressure drop.

Design and control algorithm of dual switch forward DC/DC converter with DSP digital control

On the basis of DSP digital signal processing chip TMS320F2812 function as the main control chip of power supply, this paper proposes a dual switch forward topology with RCC converter as auxiliary power supply,the bootstrap drive chip IR2110 as power drive circuit, a dual closed loop control strategy with voltage outer loop and current inner loop, and PID control algorithm using integral separation together with dead zone control. The experimental result show that the power supply structure is easy to operate, and the corresponding control strategy and algorithm effectively improve the stability of the power supply output voltage and the rapidness of the response of the system.

Digital CRISPR/Cas-Assisted Assay for Rapid and Sensitive Detection of SARS-CoV-2.

The unprecedented demand for rapid diagnostics in response to the COVID‐19 pandemic has brought the spotlight onto clustered regularly interspaced short palindromic repeats (CRISPR)/CRISPR‐associated systems (Cas)‐assisted nucleic acid detection assays. Already benefitting from an elegant detection mechanism, fast assay time, and low reaction temperature, these assays can be further advanced via integration with powerful, digital‐based detection. Thus motivated, the first digital CRISPR/Cas‐assisted assay—coined digitization‐enhanced CRISPR/Cas‐assisted one‐pot virus detection (deCOViD)—is developed and applied toward SARS‐CoV‐2 detection. deCOViD is realized through tuning and discretizing a one‐step, fluorescence‐based, CRISPR/Cas12a‐assisted reverse transcription recombinase polymerase amplification assay into sub‐nanoliter reaction wells within commercially available microfluidic digital chips. The uniformly elevated digital concentrations enable deCOViD to achieve qualitative detection in <15 min and quantitative detection in 30 min with high signal‐to‐background ratio, broad dynamic range, and high sensitivity—down to 1 genome equivalent (GE) µL−1 of SARS‐CoV‐2 RNA and 20 GE µL−1 of heat‐inactivated SARS‐CoV‐2, which outstrips its benchtop‐based counterpart and represents one of the fastest and most sensitive CRISPR/Cas‐assisted SARS‐CoV‐2 detection to date. Moreover, deCOViD can detect RNA extracts from clinical samples. Taken together, deCOViD opens a new avenue for advancing CRISPR/Cas‐assisted assays and combating the COVID‐19 pandemic and beyond.

RETRACTED: Adum3210 chip based design of the control system of water lifting irrigation based on the internet of things

In the control system of water lifting irrigation of wind power generation, the communication line is open line, and there are many auxiliary equipment nearby, which makes the control system vulnerable to external interference and causes the control system to have poor stability. For this reason, the design of the control system based on the Internet of things is proposed. The Internet of things technology is introduced to design the GPRS network part of the controller. The GPRS network module is connected with the microcontroller to improve the system performance by using the network to drive the irrigation equipment; According to the power consumption of the collector, the power of the photovoltaic cell and the capacity of the lithium polymer cell suitable for the system are obtained, and the solar power supply module is designed; Taking max13052 chip as the core, combined with Dual Digital Isolator adum3210 chip, the can interface is designed by programming its corresponding pin. Based on the hardware environment, the system control software is designed. The speed of the three-phase asynchronous motor is controlled by the frequency conversion vector, and the real-time control is achieved by the Quasi-Z source inverter. The experimental results show that under the condition of gust wind speed and step wind speed, the anti-interference performance of the control system in this paper is strong, and the energy consumption is low, which has certain feasibility.

A rapid nucleic acid concentration measurement system with large field of view for a droplet digital PCR microfluidic chip.

Droplet digital polymerase chain reaction (ddPCR) is an effective technique, with unparalleled sensitivity, for the absolute quantification of target nucleic acids. However, current commercial ddPCR devices for detecting the gene chip are time consuming due to complex image stitching. To address this issue, we propose a universal concentration determination system and realize one-time gene chip imaging with high resolution. All the functional units are controlled by self-developed software using the PyQt5 module in Python. Without stitching technology, images of the ddPCR chip (28 mm × 18 mm) containing 20 000 independent 0.81 nL micro chambers can be obtained in less than 15 seconds, which saves about 165 seconds. A white laser light source (2 mW cm-2) was employed as a substitute for the mercury lamp. Its wavelength matches well with typical fluorescent dyes (e.g., HEX, ROX and Cy5), and thus it can strengthen the fluorescence intensity for weak signals. The results also demonstrated that the correlation coefficient for the measured concentration and theoretical value was above 99%, by testing the ddPCR products with COVID-19 virus. Such a system can greatly reduce the time required for image acquisition and DNA concentration determination, and thus is able to speed up the lab-to-application process for ddPCR technology.

High speed energy efficient multiplier for signal processing

In digital signal processors, computation intensive arithmetic functions such as image smoothing, convolution and filtering frequently involve multiplication-based operations like inner-product generation and accumulation. Multiplication time is the predominate element in determining the execution time of any digital signal processing chip. Switching activity of the functional units in the multiplier contributes to significant amount of power dissipation. This paper presents high speed energy efficient multiplier. By reducing the switching activity and number of computations, the proposed multiplier achieves a better performance in terms of delay and PDP. The proposed high speed energy efficient multiplier is designed using Verilog-HDL and synthesised using Cadence RTL compiler with respect to 180 nm and 90 nm technological libraries. The proposed multiplier shows the delay reduction of 8.95% to 31.40%. The potential benefit of reducing the delay realises a PDP reduction of 13.66% to 26.95%. The performance of the proposed multiplier is verified by implementing it in 16 tap 16-bit coefficient band pass finite impulse response filter. The multiplier used here can be used in signal processing application to obtain energy efficient hardware.

Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique

This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple operation modes i.e. coarse, fine, and retention for high efficiency and transient enhancement. The proposed hybrid DF-LDO uses arrays of PMOS transistors in coarse and fine mode whereas in retention mode, only one comparator and NMOS are active and digital controller goes into the sleep mode. This results in the reduction of the power consumption and improves the output voltage ripples. In the retention mode, minimum number of blocks operate that reduces the current consumption as compared to coarse and fine modes. To further reduce the current consumption, the comparator with hysteresis is used. The proposed circuit is designed using CMOS 55 nm process. The input voltage range is from 0.8 ~ 1.5 V and the measured output voltage range is 0.756 ~ 1.456 V. The measured line regulation is 6 mV / V, and the regulation starts when the input voltage is 0.8 V. The measured load regulation is 2.3 mV/mA for maximum load current of 5 mA. The peak current efficiency of the proposed DF-LDO is 99.996 % with a maximum output voltage ripples value of 1.9 mV. The proposed digital LDO regulator active chip area is 0.012 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Design of a CMOS Lineal Hall Sensor Front‐End Working in Current Mode with Programmable Gain Stage for Power Specific Chip

With the continuous intelligentization of power systems, the demand for the integration of digital chips and sensor chips such as the Internet of Things is also increasing. A CMOS lineal magnetic Hall sensor front‐end working in current mode with programmable gain stage is designed and implemented with SMIC 55 nm standard CMOS technology. By using a spinning‐current technique, chopper technique, and digital calibration technique to eliminate the offset voltage and nonlinearity, this magnetic Hall sensor can be easily integrated into digital systems like SoCs. This work has already finished the circuit simulation and layout design, and all simulation indicators basically reach the expected value. The maximum gain of proposed sensor systems can be up to 33.9 dB. The total power is less than 4 mW. And the total area is less than 0.113 μm2. The magnetic Hall sensor can be easily integrated into chips such as the power Internet of Things to form a single‐chip‐level SoC design, which is mainly used in applications such as circuit breakers and electric energy measurement.

Droplet three-dimension manipulation in parallel liquid-infused membrane plates configuration

Abstract In this paper, we demonstrated the droplets three-dimension (3D) manipulation between a pair of parallel liquid-infused membrane plates with patterned electrodes by programmably controlling electrical direct current signals. The asymmetric electrowetting behaviors of droplet between the parallel slippery liquid-infused porous surface (SLIPS) plates configuration were investigated firstly. The droplet tends to move from the higher potential plate to the lower potential plate. The transport of the deionized water droplet in the vertical direction with electrostatic force was investigated in detail subsequently. A model was developed to study the dynamic transport behavior of the droplet movement in the vertical direction. It is found the droplet velocity increases with time, while tends to a maximum value due to the increase of drag force. We also experimentally demonstrated the droplet was driven accelerated from the higher potential plate to the lower one, and the transport time exponentially decreases with the increase of applied voltage. However, note that the excessive applied voltage would cause irregularly jumping of droplets between two plates. The applied voltage range for driving a 0.5 μl droplet was determined experimentally with various parallel-plate spacings. Finally, we demonstrated the 3D manipulation of one droplet and two droplets in two parallel plates configuration with patterned electrodes by the hybrid forces, namely, by asymmetric electrowetting force in the horizontal direction and by electrostatic force in the vertical direction. The 3D droplet manipulation on SLIPS provides a promising solution for high-throughput analysis and integrated device with high density on the digital microfluidic chip.

Vertical Noise Reduction in 3-D Mixed-Signal Integrated Circuits With Graphene Nanoribbon and Carbon Nanotube Interconnects

This study presents the analysis and reduction of vertical crosstalk in mixed-signal 3-D integrated circuits (3-D ICs) with multilayer graphene nanoribbon (MLGNR) and multiwall carbon nanotube (MWCNT) interconnects. The 14-nm technology node is considered for both digital and analog tiers. The assessments are conducted regarding the scattering parameters (S-parameters) for the equivalent circuit model of the transmission lines using the Advanced Design System (ADS) tool. Our studies demonstrate that the MLGNR transmission lines lead to lower mismatch, insertion loss, and vertical crosstalk than their MWCNT counterparts. The results show that using MLGNR improves the area overhead by more than 67% for analog and digital wires. Moreover, our model shows that the vertical noise between the analog and digital tiers is reduced by 1 and 1.62 dB when the intermediate substrate thickness increases from 20 to 30 and 40 μm. The results demonstrate that the perpendicular routing of the MLGNR interconnects reduces the vertical noise by 6.1 dB. Moreover, a 9.21-dB reduction in the vertical coupling is achieved using vertical MLGNRs in the analog IC. Our results also show that using graphene as a shield between the analog and digital chips significantly suppresses the vertical noise between the tiers, and it becomes more effective by increasing the number of graphene layers. According to our results, using one-, two-, and three-layer graphene-shield layers reduces the vertical crosstalk by 10.1, 14.9, and 19.2 dB, respectively. Moreover, the HSPICE simulations demonstrate that the MLGNR interconnects have a lower delay, power, and energy consumption than their MWCNT counterparts in the 3-D mixed-signal architecture.

A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS

A binary neural network (BNN) chip explores the limits of energy efficiency and computational density for an all-digital deep neural network (DNN) inference accelerator. The chip intersperses data storage and computation using computation near memory (CNM) to reduce interconnect and data movement costs. It performs wide inner product operations to leverage parallelism inherent in DNN computations. The BNN chip leverages lightweight pipelining at a near-threshold voltage (NTV) to reduce the overhead of sequential elements. It employs optimized data access patterns to reduce memory accesses for convolutional operation with pooling layers. The combination of these techniques enables the BNN chip to achieve a peak energy efficiency of 617 TOPS/W. The digital BNN chip approaches the energy efficiency of analog in-memory techniques while also ensuring deterministic, scalable, and bit-accuracy operation. Moreover, the all-digital design leverages process scaling and does not require additional memory transistors or passive devices to attain a peak compute density of 418 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a memory density of 414 KB/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The binary design is extended to enable bit-serial integer precision operation with a reconfigurable 1-b multiplication circuit and element-wise partial sum shift and accumulate. This technique allows for fine-grain mixed precision and retains energy efficiency by exploiting parallelism inherent in DNNs. The bit-serial binary operation allows for bit-accurate operation and high DNN accuracy that multibit analog compute-in-memory designs struggle to attain. It provides favorable energy tradeoffs compared with small-integer digital DNN accelerators.

High-throughput and uniform large field-of-view multichannel fluorescence microscopy with super-thin dichroism for a dPCR gene chip

With the rapid development of digital precision medicine, the digital polymerase chain reaction (dPCR) deoxyribonucleic acid (DNA) gene chip integrates more channels with smaller size and larger area, which leads to a higher technical requirement for commercial optical fluorescence microscopy. The multitime image splicing method is widely used for DNA detection. However, it consumes time and has visible seamless image results. This work has demonstrated the design and fabrication of a three channel reversed and reduced fluorescence microscopic imaging system with high-resolution and large field of view for one-time imaging. We introduced the super ultra-thin dichroic mirror into the space between the objective lens and the gene chip to achieve a uniform illumination and a strong signal for the large area gene chip. The fabricated new fluorescence microscopy can take a one-time imaging for the 28×18mm dPCR gene chip with more than 20,000 multi micro-droplets within FAM, HEX, and ROX fluorescence channels. The optical system was designed with a numerical aperture (NA) of 0.106. Modulation transfer function (MTF) is higher than 0.675 at 70 lp/mm, and the function resolution capability is 10 µm with the whole magnification of -0.65times. The fly's eye lens-based illumination system was tested with a uniform output of over 90% in the whole ϕ34.7mm chip area. The design was tested, and the experimental results showed that this new system provides a fast, efficient, and professional optical imaging method for detection of the new emerged digital PCR gene chip, which has larger area and more channels.

Neuromorphic on-chip recognition of saliva samples of COPD and healthy controls using memristive devices

Chronic Obstructive Pulmonary Disease (COPD) is a life-threatening lung disease, affecting millions of people worldwide. Implementation of Machine Learning (ML) techniques is crucial for the effective management of COPD in home-care environments. However, shortcomings of cloud-based ML tools in terms of data safety and energy efficiency limit their integration with low-power medical devices. To address this, energy efficient neuromorphic platforms can be used for the hardware-based implementation of ML methods. Therefore, a memristive neuromorphic platform is presented in this paper for the on-chip recognition of saliva samples of COPD patients and healthy controls. Results of its performance evaluations showed that the digital neuromorphic chip is capable of recognizing unseen COPD samples with accuracy and sensitivity values of 89% and 86%, respectively. Integration of this technology into personalized healthcare devices will enable the better management of chronic diseases such as COPD.

Phase Voltage-Oriented Control of a PMSG Wind Generator for Unity Power Factor Correction

This paper presents the power factor control of a permanent magnet synchronous wind generator (PMSG) wind turbine using a phase voltage-oriented control (PVOC) scheme, which is different from the conventional rotor flux-oriented control (RFOC) method and without using a rotor position sensor or sensorless estimator. The proposed control system is operated in two separately synchronously rotating d-q frames. One is for a phase-locked loop (PLL) and the other is for the PVOC current control loop. A PI controller functioned as a low-pass filter in the PLL loop is designed for extracting the phase voltage angle for the coordinate transformation between the stationary α-β frame and the synchronously rotating d-q frame in the PVOC control loop. The d-q modeling of the PMSG with the three-phase voltage vector aligned on the d-axis is then derived and based on which an another PI controller followed by decoupling control is designed, so that the three-phase currents are in phase with the three-phase output voltages of the wind generator for unity power factor correction. The simulation results in PSIM show the performance of the proposed control system which is also experimentally verified by using a TI TMS320F28335 digital control chip.

The design of permanent magnet variable-frequency door-motor with one-driver dual control

Aiming at the scarcity for matched high-end door-motor to domestic high-velocity elevator market, with the research on domestic and overseas elevator door-motor control technology and permanent magnet synchronization technology, a high-end door-motor system that matched with high-velocity elevator and even ultra-high-velocity elevator has been put forward. It introduced in detail about the door-motor control hardware design that used digital chips and intelligent power module as its main circuit, how to realize the door-motor operation curve with SVPWM (Space Vector Pulse Width Modulation), the orientation angle learning method of permanent magnet synchronization motor, how to work in parallel for dual-motor and how to switch the single motor as well as the overall mechanical design scheme. The actual door-motor operation curve has been surveyed through experiment and the operation curve has been analyzed. The research results indicate that the door-motor system can suffice the design requirements input and the design scheme is reasonable and reliable, which will not only significantly shorten the opening and closing time compared to the ordinary door-motor and distinctly improve the service efficiency of high-velocity elevator, but also make the operation curve of the door-motor more graceful, quieter, more stable and safer.

Training deep neural networks for wireless sensor networks using loosely and weakly labeled images

Although deep learning has achieved remarkable successes over the past years, few reports have been published about applying deep neural networks to Wireless Sensor Networks (WSNs) for image targets recognition where data, energy, computation resources are limited. In this work, a Cost-Effective Domain Generalization (CEDG) algorithm has been proposed to train an efficient network with minimum labor requirements. CEDG transfers networks from a publicly available source domain to an application-specific target domain through an automatically allocated synthetic domain. The target domain is isolated from parameters tuning and used for model selection and testing only. The target domain is significantly different from the source domain because it has new target categories and is consisted of low-quality images that are out of focus, low in resolution, low in illumination, low in photographing angle. The trained network has about 7 M (ResNet-20 is about 41 M) multiplications per prediction that is small enough to allow a digital signal processor chip to do real-time recognitions in our WSN. The category-level averaged error on the unseen and unbalanced target domain has been decreased by 41.12%.