Digital Calibration Technique Research Articles

A 6bit, 7mW, 700MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation

SUMMARY A 6-bit, 7 mW, 700 MS/s subranging ADC using Capacitive DAC (CDAC) and gate-weighted interpolation fabricated in 90 nm CMOS technology is demonstrated. CDACs are used as a reference selection circuit instead of resistive DACs (RDAC) for reducing settling time and power dissipation. A gate-weighted interpolation scheme is also incorporated to the comparators, to reduce the circuit components, power dissipation and mismatch of conversion stages. By virtue of recent technology scaling, an interpolation can be realized in the saturation region with small error. A digital offset calibration technique using capacitor reduces comparator’s offset voltage from 10 mV to 1.5 mV per sigma. Experimental results show that the proposed ADC achieves a SNDR of 34 dB with calibration and FoM is 250 fJ/conv., which is very attractive as an embedded IP for low power SoCs.

A fast foreground digital calibration technique for pipelined ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.

A Dither-Less All Digital PLL for Cellular Transmitters

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 108 dBc/Hz, an out-of-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 160 dBc/Hz @20 MHz and in-band fractional spurs below <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 50 dBc. These results are obtained for an output carrier of 1.8 GHz, a reference clock of 26 MHz, with a power consumption of 41.6 mW.

Successive-divider-line ADC dedicated to low-power medical devices

A low-power and small silicon area digitally controlled Switched Mode Power Supply (SMPS) is intended for the minimization of both power and size of an on-chip DC power supply building block which is mainly dedicated for implantable medical sensing and microstimulation devices. Such SMPS is based on a successive divider-line analog-to-digital Converter (SDLADC), which is the focus of this paper. Special attention is paid for reducing the power consumption and silicon area of this SDLADC, which consists of a resistor network based on diode connected transistor used to replace the delay-line of the windowed ADC. To compensate process and temperature variations, a digital calibration technique is used to meet the specified static and dynamic output voltage regulations and avoid variations of the regulated SMPS output voltage. The proposed ADC is implemented in AMS 0.35μm CMOS process. Simulation results show a current consumption of 1.5μA/MHz and conversion time of 10ns much lower than recent conventional topology values. The proposed circuit exhibits a quantization steps smaller than 1.6% of Vref and it can be a solution for high switching frequency, which results on faster regulation of SMPS output voltage.

Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering

A digital background calibration technique based on comparator dithering is proposed to correct the nonlinear errors resulting from capacitor mismatches, finite opamp gain, and other nonlinearities. It changes the threshold levels of sub analog-to-digital converters (ADCs) according to a pseudorandom noise sequence. In our scheme, except adding multiplexers, the analog circuits need no modification. The first- and third-order errors are measured and corrected in digital domain. In order to reduce the input interference, adaptive digital windows which need no extra analog circuits are presented. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-and-distortion ratio is increased from 59 to 84 dB and the spurious-free dynamic range is increased from 62 to 105 dB, in a 14-bit pipelined ADC with 0.2% capacitor mismatches and 60-dB nonideal opamp gain.

Exploiting Process Variation and Noise in Comparators to Calibrate Interstage Gain Nonlinearity in Pipelined ADCs

This paper presents a digital background calibration technique that intentionally exploits process variation and noise in comparators to correct conversion errors caused by interstage gain error, gain nonlinearity, and capacitor mismatch in pipelined ADCs. The merits of this technique lies in its design simplicity, fast convergence speed, and low power. Simulation results are presented for a 12-bit pipelined ADC, similar to that described by Murmann and Boser [28], and Keane et al., [29] using low-gain amplifiers. With calibration, the SNDR and SFDR are improved from 47 and 49 dB to 72 and 92 dB, respectively. The number of conversions required for convergence is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , which is about 4 times faster than that of Keane et al. and 40 times faster than that of Murmann and Boser.

Digital DAC calibration technique for and incremental modulators

A new digital nonlinearity calibration and correction technique is proposed for multi-bit DACs in ΔΣ and incremental modulators. By finding the differences between capacitance errors using the ΔΣ modulator, the integral nonlinearity of the DAC can be found, and corrected digitally.

An Interpolation-Based Calibration Architecture for Pipeline ADC With Nonlinear Error

The linearity of a pipeline analog-to-digital converter (ADC) is mainly limited by capacitor mismatch and finite operational amplifier (OPAMP) gain, which cause large power and design difficulty in modern nanometer CMOS processes for high-resolution pipeline ADCs. It is a trend of developing digital calibration techniques to compensate the analog error in pipeline stages. This paper systematically introduces a novel interpolation-based digital calibration architecture to compensate both linear and nonlinear errors from pipeline stages. The new method does not require convergence. The effect of calibration error is analyzed in detail in this paper. A prototype 20-MS/s pipeline ADC is fabricated in a 0.35-μm 3.3-V CMOS process. For 12-b resolution, the digital calibration improves the ADC differential nonlinearity and integral nonlinearity from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590-kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio and spurious-free dynamic range from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB, respectively. With the new calibration technique, low-gain OPAMPs and small capacitors are used in the pipeline. The designed ADC has 0.78-pJ/step figure of merit (FOM), which is among the lowest reported FOMs for high-resolution pipeline ADC designs. The new architecture requires an accurate calibration ADC (CalADC) and two digital decoders. CalADC is implemented on-chip with 6.5% die area and 8.9% power. The decoders are synthesized to have 912 gates and consume 23.4% ADC power.

Electromagnetic Interference Analysis in HV Substation Due to a Static Var Compensator Device

Static var compensator (SVC) devices have been extensively utilized in modern substations to achieve high flexibility and wide tolerance to load variation. However, due to frequent switching of the thyristors in a static var compensator, large amounts of electromagnetic interference (EMI) are being generated, which may cause malfunction of the SVC or unaccepted response of victim devices positioned nearby. In this paper, an advanced acquisition system was established to implement onsite measurements in order to obtain the EMI data. A digital calibration technique for the antenna was applied to trace back the actual electromagnetic emissions. The radiated and conducted EMI data are comparatively analyzed to present detailed and useful information of the EMI levels. According to the configuration of an SVC and the dynamic performance of the random load, an equivalent model was established to simulate and predict the conducted EMI levels. Based on onsite measurements as well as theoretical analysis, pertinent immunity measures were put forward to reduce coupling impacts on the electronic units of the secondary side.

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration

This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area in a 0.13-μm CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.

Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs

An efficient two-phase calibration technique for 1-bit/stage pipelined Analog---to---Digital Converters (ADCs) is presented in this paper. The proposed technique employs linear histogram testing to collect the required information to calibrate the non-ideal ADC output behavior induced by capacitor mismatch and comparator offset. In the first phase, it calibrates the missing-decision-level errors by amplification gain reduction. Unlike previous works, which require large capacitor arrays, only few switches are added to the circuit. The second phase eliminates missing-transition levels (missing codes). It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both static and dynamic performances.

A 14 bit 200 MS/s DAC With SFDR &gt;78 dBc, IM3 &lt; -83 dBc and NSD &lt;-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence of current cells to reduce the dynamic integral nonlinearity in an I-Q domain, the DMM technique digitally calibrates all mismatch errors so that both the DAC static and dynamic performance can be significantly improved in a wide frequency range. Compared to traditional current source calibration techniques and static-mismatch mapping, DMM can reduce the distortion caused by both amplitude and timing mismatch errors. Compared to dynamic element matching, DMM does not increase the noise floor since the distortion is reduced, not randomized. The DMM DAC was implemented in a 0.14 μm CMOS technology and achieves a state-of-the-art performance of SFDR >; 78 dBc, IM3 <; -83 dBc and NSD <; -163 dBm/Hz in the whole 100 MHz Nyquist band.

A robust and simple two-mode digital calibration technique for pipelined ADC

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters (ADC). The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom (PN) sequence injection capacitors at the ADC initialization, while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation. The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain, but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors. The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology. The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process. Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage, the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB, respectively. With the calibration, the maximum integral nonlinearity (INL) of the ADC reduces from 4.75-LSB to 0.65-LSB, while the ADC core consumes 82-mW at 3.3-V power supply.

A nonlinearity error calibration technique for pipelined ADCs

This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.

카운터 기반 디지털 보상 기법을 이용한 위상 고정 루프

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 ㎓ charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate 0.5㎂ current mismatch in CP. It was designed in a standard 0.13㎛ CMOS technology. The maximum calibration time is 33.6μs and the average power is 18.38㎽ with 1.5V power supply and effective area is 0.1804㎟.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Therefore, it uses less area than comparable conventional delta-sigma modulators, and the architecture is well-suited to IC processes optimized for fast digital circuitry. The prototype IC is implemented in 65 nm LP CMOS technology with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8-17 mW, 0.5-1.15 GHz, 3.9-18 MHz, and 67-78 dB, respectively, and an active area of 0.07.

Application of Subharmonic Injection Locking of LC Oscillators to LO-Based Phase-Shifting Phased-Array Architectures

A ninth-subharmonic injection-locking scheme is proposed for local oscillator (LO) phase-shifting-based phased-array architectures operating in the ISM band at 24 GHz. The presented architecture employs a phase-shifter at the ninth subharmonic, a high-speed regenerative comparator, and a negative-gm oscillator to synthesize multiple phases of ninth-harmonic LO signals from a 2.41-GHz reference at the destination and in close proximity to the RF/millimeter-wave front-end mixers with first LO at 21.69 GHz. A digital phase-shift calibration technique is discussed. The reported LO phase-shifting and synthesis scheme is implemented in IBM's 130-nm CMOS technology and consumes a total of 32 mA per LO element from a 1.2-V supply. The injection-locked oscillators have a phase-noise performance of - 107.17 dBc/Hz at 1-MHz offset from 21.51 GHz. The maximum phase-shift error at 21.69 GHz is 9.86° and 2.1° before and after calibration, respectively.

A 10-b 50-MS/s 820-$\mu $W SAR ADC With On-Chip Digital Calibration

This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm(2) .

A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion

A nonlinear adaptive digital calibration technique for multistage analog-to-digital converters (ADCs) is presented. The approach is derived from a replica-path scaling principle inspired by the parallel-ADC equalization architecture. The treatment of residue gain nonlinearities leads to potentially significant power savings for a simple modification of the first ADC stage. The design tradeoffs involved in this technique, particularly a band-limited interpolator employed, are discussed in detail. Computer simulations demonstrate signal-to-noise-plus-distortion-ratio and spurious-free-dynamic-range improvements from 40 to 90 dB and 45 to more than 100 dB, respectively, for a 15-bit pipelined ADC.