Digital Error Correction Research Articles

Real-time digital error correction for flash analog-to-digital converter

We have designed, fabricated and successfully tested digital error-correction circuits to improve the performance of superconductive flash analog-to-digital converters (ADCs). The comparators coding the most significant bits (MSBs) are the least sensitive to the input signal, and therefore have the most threshold errors due to jitter and threshold misplacement. These errors are completely eliminated by implementing an ADC architecture using two comparators per bit, and employing logic to encode bit N by looking back to the state of the (N-1) bit. In this way, all code transitions are derived from the least significant bit (LSB) comparators. The MSB comparators are used only to encode the LSB data.

The Organization of Brain Activations in Number Comparison: Event-Related Potentials and the Additive-Factors Method

Measuring reaction times (RTs) using the additive-factors method provides information about the sequence of processing stages in a cognitive task. Here, I describe how the simultaneous recording of event-related potentials (ERPs) in the same task can provide complementary information that cannot be obtained using RTs alone. Most notably, ERP data can reveal the absolute activation time and the coarse brain localization of processing stages. RTs and ERPs can also be used to cross-validate a serial-stage model. These notions were applied to a study of the temporal unfolding of brain activations in a number comparison task. ERPs were recorded from 64 scalp electrodes while normal subjects classified numbers as larger or smaller than 5. Specific scalp signatures and timing data were obtained for stages of word and digit identification, magnitude comparison, response programming, and error capture and correction. The observed localizations were compatible with previous neuropsychological and brain imaging data and provided new insights into the cerebral lateralization and timing of number processing.

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC

This paper discusses fully digital error correction and self-calibration which correct errors due to capacitor mismatch, charge injection, and comparator offsets in algorithmic A/D converters. The calibration is performed without any additional analog circuitry, and the conversion does not need extra clock cycles. This technique can be applied to algorithmic converter configurations including pipelined, cyclic, or pipelined cyclic configurations. To demonstrate the concept, an experimental 2-stage pipelined cyclic A/D converter is implemented in a standard 1.6-/spl mu/m CMOS process. The ADC operates at 600 ks/s using 45 mW of power at /spl plusmn/2.5 V supplies. The active die area excluding the external logic circuit is 1 mm/sup 2/. Maximum DNL of /spl plusmn/0.6 LSB and INL of /spl plusmn/1 LSB at a 12-b resolution have been achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS

A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1- mu m CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz. >

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 12-b 5-Msample/s two-step CMOS A/D converter

Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1- mu m CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm * 3.7 mm. >

An algorithm for scaling and single residue error correction in residue number systems

An algorithm for scaling and single residue digit error correction is proposed. This algorithm is fully based on mixed radix conversion (MRC). The redundant digits of MRC can be used to establish a lookup table to correct single residue digit errors. By using this algorithm the error correction and scaling operation can be unified in one hardware, thereby reducing the complexity of these implementations. The scaling error e/sub s/ is analyzed and found to be limited to the interval of -1 >

Error correction techniques for high-performance differential A/D converters

Error correction techniques that overcome several error mechanism that can affect the accuracy of charge-redistribution analog-to-digital converters (ADCs) are described. A correction circuit and a self-calibration algorithm are used to improve the common-mode rejection of the differential ADC. A modified technique is used to self-calibrate the capacitor ratio errors and obtain higher linearity. The residual error of the ADC due to capacitor voltage dependence is minimized using a quadratic voltage coefficient (QVC) self-calibration scheme. A dual-comparator topology with digital error correction circuitry is used to avoid errors due to comparator threshold hysteresis. A fully differential charge-redistribution ADC implemented with these techniques was fabricated in a 5-V 1- mu m CMOS process using metal-to-polysilicide capacitors. The successive-approximation converter achieves 16-b accuracy with more than 90 dB of common-mode rejection while converting at a 200-kHz rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f/sub T/. 3- mu m-rule standard bipolar technology. Its die size is 25 mm/sup 2/, and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5 degrees .< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Multibit oversampled Σ-Δ A/D convertor with digital error correction

This now famous anthology brings together various aspects of oversampling methods and compares and evaluates design approaches. It describes the theoretical analysis of converter performances, the actual design of converters and their simulation, circuit implementations, and applications.

A 14-bit 10- mu s subranging A/D converter with S/H

A microprocessor-compatible, 14-bit, 10- mu s subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated. >

A 12-bit successive-approximation-type ADC with digital error correction

A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D converter utilizing the same analog chip but a conventional digital chip without error correction. A speed improvement from 12 to 7 /spl mu/s was obtained with digital error correction.

Analog-digital converter of infralow-frequency signals with digital error correction

Analog-digital converter of infralow-frequency signals with digital error correction

Error Detection and Correction by Product Codes in Residue Number Systems

The arithmetic error detecting and correcting capabilities of product (AN) codes in residue number systems (RNS) are described. The redundancy necessary and sufficient to allow single residue digit error detection or correction is determined, under the hypothesis that the error affects either an arbitrary legitimate number or a number in overflow. It is shown that single-bit errors are also correctable, provided that the residue digits are conveniently encoded. Two different approaches to this problem are discussed. Simple procedures for error detection and correction are presented, and it is shown that the additive overflow detection is a by-product of such procedures. Proofs and examples are given.