Abstract
A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D converter utilizing the same analog chip but a conventional digital chip without error correction. A speed improvement from 12 to 7 /spl mu/s was obtained with digital error correction.
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