Diffused Resistors Research Articles

A 2-V 23-μA 5.3-ppm/°C curvature-compensated CMOS bandgap voltage reference

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.

A four-terminal compact model for high voltage diffused resistors with field plates

This paper presents a four-terminal, physically based, high-voltage diffused resistor model. The model accounts for depletion, inversion, and accumulation at the surface due to the MOS effect of metal field plates, as well as the depletion pinching effect at the sides and bottom of the diffused resistor.

Electric drift of the bridge offset for pressure sensors and its utilization

This paper shows that electric drift of bridge offset for pressure sensors exists as well as thermal drift and this phenomenon results from the dependence of non-linear diffused resistors upon the bridge voltage. Electric drift can be used for compensating offset thermal drift.

Modeling of voltage-dependent diffused resistors

A voltage-dependent diffused resistor model has been developed using conventional voltage controlled current sources (VCCSs) defined by a two-dimensional polynomial for simulations of mixed-signal circuits. The polynomial coefficients can be defined by a simple first order polynomial which can be a function of geometry and process variables to accurately reflect the manufacturing process. Alternatively, a conventional junction field effect transistor (JFET) model can be used to represent voltage dependence of the diffused resistor.

Spiral junction termination

A new junction termination structure composed of a decreasing width spiral diffused resistor connecting anode and cathode region is presented. Leakage current through the spiral resistor results in optimized voltage distribution between the spiral turns which effectively reduces high electric field at the anode junction curvature. By circuit mode device modeling approach, the influence of several design parameters of importance on the breakdown properties were investigated. A major concern was shown to be the possibility of a premature reach-through between the spiral turns, resulting in increased leakage current and soft breakdown characteristics. A design with nonuniform spiral width and optimized spacing between the spiral turns is proposed, enabling almost ideal breakdown voltages with reduced spiral leakage current and eliminated reach-through between the spiral turns. Low susceptibility to oxide charges is confirmed by irradiation test, showing improvement of breakdown properties after irradiation. Further improvement in operation is obtained by a floating spiral structure due to spiral resistance limiting the increase of the multiplication induced current through the spiral. In comparison with common termination structures the spiral junction termination offers simple design and processing, close to ideal breakdown voltages and high reliability of operation.

Compensation of sensitivity shift in piezoresistive pressure sensors using linear voltage excitation

Abstract When the temperature increases, the output voltage from a silicon piezoresistive sensor will decrease when the excitation voltage to the sensor element is kept constant. This is due to the temperature dependence of the piezoresistive effect. Compensation of this effect can be achieved by either increasing the voltage excitation or by increasing the amplification of the output signal from the sensor with increasing temperature. This article discusses the method of increasing the voltage excitation linearly with temperature. Analysis shows that the sensitivity shift can be reduced to less than 0.6% within the temperature range − 30 to + 100 °C if the excitation voltage has a proper temperature coefficient. This has been experimentally verified for two different sensor types. The first type uses thin-film deposited polysilicon resistances, and the second type uses diffused resistors. Without compensation the sensitivity shifts for the chosen sensor types are 7 and 16%, respectively in this temperature range.

Potential for a smart sensor based on an integrated silicon anemometer

Abstract An intelligent silicon anemometer is being developed with a bridge which employs diffused resistors operated at an elevated temperature to achieve a high dynamic range. A novel technique achieves thermal feedback in a double Wheatstone bridge configuration using integrated temperature-insensitive operational amplifiers. The aim is to achieve high sensitivity, immunity from humidity and from ambient temperature variations. Early devices have been fabricated in CMOS technology demonstrating the efficient implementation of high performance analogue electronics suitable for using low-cost standard IC fabrication processes. An application for this integrated smart silicon anemometer is to replace the more cumbersome mechanical peak-flow meters used in the treatment of sufferers of chronic obstructory pulmonary diseases [1]. The reliability and immunity from interference can be further improved by integrating the complete sensor system on a single monolithic CMOS or BiCMOS chip.

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.

A synthesis of ESD input protection scheme

A synthesis of total effective input protection, consisting of primary and secondary protection devices, is presented here for advanced CMOS technologies. In particular, it is shown that for efficient protection the primary circuit needs to be a low trigger SCR and the secondary circuit needs to be either a diffusion resistor with avalanche suppression or even a polysilicon resistor. The latter scheme with the poly resistor is shown to give greater than 6 kV of reliable performance, which can be particularly attractive for analog circuit applications.

A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 mu /sup 2/, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +or-1 and +or-10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies. >

DARSI: RC data reduction (VLSI simulation)

Taking into account RC effects in VLSI simulation and verification systems, without seriously degrading their efficiency, requires preliminary data reduction. A tool, DARSI (data reduction system for interconnects), that can handle both polysilicon and diffusion resistive effects is presented. It contains the reduction scheme described by S.-L. Su et al. (Proc. IEEE Conf. Computer-Aided Design, p.270-3, 1986), a novel line-based reduction method, a novel loop reduction scheme, and a technique for identifying important diffusion resistors. The number of parasitic elements is considerably reduced, while guaranteeing delay errors to be less than a few percent. DARSI is implemented in a general-purpose rule-based verification environment for VLSI and has a nearly linear complexity. Application to several practical designs is also discussed. >

Diffused resistors characteristics at high current density levels-analysis and applications

Both heavily (source-drain) and lightly (well) doped diffused resistors used in modern CMOS integrated-circuit technologies are studied under high current density levels. The effects of high-field mobility degradation, space-charge limited-current, and charge-depletion narrowing (pinchoff) are discussed, and the related analytical solutions are derived and characterized. The applicability of the study to electrostatic discharge (ESD) protection networks, latchup protection circuitry, and output noise suppression resistors is addressed. Velocity saturation due to mobility degradation is found to be the prevailing mechanism, while space-charge limiting current and depletion narrowing have only limited effect on the lightly doped ones. The resulting saturation current densities allow proper resistor designs which can effectively limit ESD and latchup current into highly susceptible nodes and thus-improve overall circuit reliability, potential suppression of I/O switching noise is also discussed and shown to be more sensitive to the ratio between peak noise and steady-state currents. The experimental data confirm the theoretically predicted saturation velocity and critical field for the lightly doped case but show substantial discrepancy for the heavily doped layer. >

A low-power easy-to-calibrate temperature transducer

This paper describes a modified IC temperature transducer with an intrinsic reference whose main features are: easy calibration (in a single step), high sensitivity over a wide temperature range (-4.6 mV//spl deg/C; -50/spl deg/C to +125/spl deg/C), low output impedance (40 /spl Omega/), and low-power dissipation (200 /spl mu/W). The device in which diffused resistors are applied has been fabricated in a conventional IC process. Its application in thermocouple cold-junction compensation is discussed.

An inherently monotonic 12 bit DAC

Describes a 12 bit DAC which uses diffused resistors and requires no trimming to guarantee monotonicity for all grades over the temperature range. The segmented ladder design, departing from the traditional R-2R approach used in virtually all high-speed high resolution converters, provides inherent monotonicity and differential linearity as high as 13 bits. Also afforded is a more uniform step size over the temperature range than the trimmed 12 bit converters. The only critical resistor matching occurs at the major carries or midpoints of each of the eight segments and the tolerances are equivalent to that of a 9 bit DAC, or eight times lower than the R-2H approach. In essence, the problem has been divided into eight separate problems, each with tolerances eight times lower than that of a 12 bit DAC. The converter has been found to be immune to variations in temperature, time, process, and mechanical stress. The circuit also features differential high compliance current outputs, wide supply range, and a multiplying input.

The Current Limiting Capability of Diffused Resistors

An experimental evaluation of the current limiting capability of dielectrically isolated diffused resistors at transient ionizing dose rates up to 6×1012 rads(Si)/ sec is presented. Existing theoretical predictions of the transient response of diffused resistors are summarized and compared to the experimentally measured values. The test resistors used allow the effects of sheet resistance and geometry on the transient response to be determined. The experimental results show that typical dielectrically isolated diffused resistors maintain adequate current limiting capability for use in radiation hardened integrated circuits.

C-MOS/SOS LSI input/Output protection networks

An improved input and output electrical surge protection has been developed for C-MOS and MNOS large-scale integrated circuitry fabricated on sapphire. The failure mode was designed to be the input- or output-series limiting diffused resistor, which can be controlled reliably through the fabrication processes. Forward-bias diodes attenuate the overvoltage surges. Failure energies and voltages have been evaluated, and design equations are developed and verified.

The effects of ionizing radiation on diffused resistors

A theoretical examination of the effects of ionizing radiation on diffused resistors performed to ascertain the feasibility of their use in hardened dielectrically isolated integrated circuits is described. The two basic effects — conductivity modulation, which is generally insignificant or can easily be rendered so, and photocurrent generation, the consequences of which essentially determine the diffused resistor hardness — are studied. Results indicate that typical dielectrically isolated diffused resistors are quite invulnerable to ionizing radiation. Design guidelines to achieve optimum hardness are implied. Initial findings of radiation experiments performed on a diffused resistor test chip are reported. When transient leakage dissociated with the resistor structures is accounted for, the results substantiate the primary conclusions of the theoretical study.

RC transmission line with nonlinear controlled parameters Small-signal characteristics

Controlled RC transmission lines can be used to model such solid-state devices as field-effect transistors and diffusion resistors; therefore, the terminal properties of such lines are important. In this paper, expressions for the transmission (chain) parameters of an arbitrary controlled RC transmission line are established.

Polycrystalline silicon resistors for integrated circuits

The suitability of thin films of doped polycrystalline silicon on SiO 2 substrates for the production of high value resistors for monolithic integrated circuits is considered. Resistors fabricated from this material posses the advantages of high sheet resistivity and dielectric isolation while still preserving an all silicon technology compatible with conventional production techniques. Relevant structural and electrical properties of doped polycrystalline films produced by both vacuum evaporation onto hot substrates with gas-doping and by diffusion-annealing of amorphous films have been investigated. Sheet resistivities and TCR values measured on 2500 Å polycrystalline films have proved superior to those encountered with conventional diffused resistors. Typically films with sheet resistivities of 1 kΩ/□ had TCR's of −1000 ppm/°C while conventional diffused resistors are generally made from material of 200 Ω/□ and +2000 ppm/°C TCR. Etched resistor line widths of 0·25 mil. have been obtained in the polycrystalline material employing conventional photolithographic techniques. The temperature stability and linearity of doped polycrystalline resistors have been investigated.

RESIST: A time sharing computer program for designing diffused resistors

The resistor design program RESIST includes correction terms due to right-angle bends, geometrical correction in the end regions due to surface crowding, and correction due to cross-sectional current crowding and the contact resistance in the contact regions. Chawla's recently published geometrical correction term is used to facilitate "one-shot" calculation of resistor length.