Differential Transimpedance Amplifier Research Articles

Design and construction of an affordable optical power meter: micro- to milli-Watt in the 400–800 nm range

This study introduces the design, construction, and evaluation of an affordable optical power meter prototype, AYR (Affordable Yet Reliable) version 1.0, which operates effectively within the 400–800 nm range, using a silicon photodiode. Aimed at bridging the gap in accessibility to precise and reliable photonics instrumentation, especially in resource-constrained settings, AYR 1.0 leverages advancements in photodiode technology, additive manufacturing, and do-it-yourself electronics. The device incorporates a custom-built electronic circuit that facilitates accurate optical power measurement by converting light into electrical current. Through rigorous testing against a reliable commercial optical power meter, AYR 1.0 demonstrated exceptional accuracy and reliability. Sensitivity values ranged from ∼13 μA mW−1 at 405 nm to ∼796 μA mW−1 at 805 nm. The operational power range spanned from 0.003 mW to 242.0 mW, with linearity (R 2) values consistently above 0.9981, indicating high fidelity in measurement. Repeatability percentages varied between 99.4% and 99.9%, and response times ranged up to 55 μs, showcasing the prototype’s rapid and reliable response to changes in optical power. The key components include a low-cost silicon photodiode (2DU10), a differential trans-impedance amplifier circuit for signal processing, and a 3D-printed housing for the sensor head and console, contributing to its cost-effectiveness and robustness. The prototype’s total cost was 116 US dollars, highlighting its affordability and potential for widespread adoption.

A multichannel thermal bubble-actuated impedance flow cytometer with on-chip TIA based on CMOS-MEMS

Electrochemical impedance spectroscopy (EIS) flow cytometry offers the advantages of speed, affordability, and portability in cell analysis and cytometry applications. However, the integration challenges of microfluidic and EIS read-out circuits hinder the downsizing of cytometry devices. To address this, we developed a thermal-bubble-driven impedance flow cytometric application-specific integrated circuit (ASIC). The thermal-bubble micropump avoids external piping and equipment, enabling high-throughput designs. With a total of 36 cell counting channels, each measuring 884 × 220 μm2, the chip significantly enhances the throughput of flow cytometers. Each cell counting channel incorporates a differential trans-impedance amplifier (TIA) to amplify weak biosensing signals. By eliminating the parasitic parameters created at the complementary metal-oxide-semiconductor transistor (CMOS)-micro-electromechanical systems (MEMS) interface, the counting accuracy can be increased. The on-chip TIA can adjust feedback resistance from 5 to 60 kΩ to accommodate solutions with different impedances. The chip effectively classifies particles of varying sizes, demonstrated by the average peak voltages of 0.0529 and 0.4510 mV for 7 and 14 μm polystyrene beads, respectively. Moreover, the counting accuracies of the chip for polystyrene beads and MSTO-211H cells are both greater than 97.6%. The chip exhibits potential for impedance flow cytometer at low cost, high-throughput, and miniaturization for the application of point-of-care diagnostics.

Increasing the accuracy of electrostatic fields strength measurement by using an improved differential transimpedance amplifier circuit

An electrostatic field mill (EFM) is widely used to measure the strength of electrostatic fields, the main drawback of which is the occurrence of large measurement errors (up to 15 % in the range from 0 to 1 kV/m). This paper examines the aspects of using transimpedance amplifiers (TIAs) for the tasks of converting the current received from the EFM sensor into voltage, which will make it possible to reduce the instrumental error and ensure the linearity of the atmospheric electrostatic field strength measurement. In the general case, for the functional circuits of the electrostatic field mill, which include a differential transimpedance amplifier, there is the use of two TIA circuits, which are connected in parallel. Despite the simplicity of implementation, such a configuration contains a number of disadvantages and is not optimal. In the paper, a comparative analysis of a typical circuit of a differential TIA and a circuit of an ungrounded differential transimpedance amplifier with zero voltage drop proposed by the authors is carried out. As a result of the analysis, it was established that the designed authentic circuit of the ungrounded differential transimpedance amplifier with zero voltage drop has better parameters of linearity and interference resistance, in contrast to the generally accepted one. The value of the signal-to-noise ratio for the proposed scheme improved by 42 % on average compared to the typical one. The main difference of the proposed scheme is that the stability of the amplification factor is ensured, the influence of the bias parameters of the operational amplifier is leveled, and the overall noise level is reduced. The use of the designed scheme of an ungrounded differential transimpedance amplifier with zero voltage drop could make it possible to increase the accuracy of the measurement of the electrostatic field strength

Design and Simulation of Low Power Differential Transimpedance Amplifier Using Degenerations Capacitors

In today’s internet-connected culture, high-speed data transmission techniques are in high demand. Optical communication is most used techniques for data transmission with speed. High-speed amplifiers are needed, nevertheless, to obtain high gains and transform current signals into voltage gains. This is accomplished via transimpedance amplifiers, a crucial component of optical receivers. In this work, a high-speed transimpedance amplifier with negative degeneration capacitors and complete differential operation is built. The proposed design has a transimpedance gain of approximately 52.4 dB at 19.8 GHz and an average input-referred noise current of roughly 23.3 pA/√Hz. The suggested circuit also has an high gain, and low input-referred noise, excellent bandwidth all of which contribute to its low power consumption of roughly 215 uW. This makes it appropriate for Internet of Things (IoT) devices, smart devices, mobile phones, laptops, and other computer peripherals.

A 12.5 Gb/s 0.13‐μm CMOS inductorless transimpedance amplifier with 1 pF input capacitance for optical communications

SummaryThis paper proposes an inductorless fully differential transimpedance amplifier (TIA) with a single‐ended photo current to offer high bandwidth for applications of beyond 10 Gb/s optical communications. The presented TIA provides a much lower input impedance by modifying the cross‐coupled regulated cascode (CC‐RGC) configuration. The introduced method is able to enhance the bandwidth in the presence of wide range of input photodiode capacitance from small to large values, with a negligible increase in the peaking of frequency response. The proposed circuit is designed and simulated using the TSMC 130‐nm CMOS technology to validate the proposed technique. The post‐layout simulation results show that the TIA delivers a transimpedance gain of 46.5 dB , a bandwidth of 8.8 GHz, and an input‐referred current noise of 33 pA/√Hz. The circuit occupies an active area of 0.004 mm2 and consumes 9.8 mW from a 1.3 V supply. Furthermore, the robustness of the proposed TIA is verified by means of the Monte Carlo simulations.

Design and simulation of differential transimpedance amplifier with active feedback for optical receivers

AbstractAn active feedback network‐based bandwidth extension technique for CMOS differential transimpedance amplifier (TIA) is proposed in 0.18 µm CMOS process technology. The design consists of three stages in differential mode. The first stage is a common‐source amplifier that minimizes noise. A common collector stage is used for level shifting and buffering in the second stage. The third stage is a differential amplifier that provides additional gain. In addition to these three stages, an active CMOS negative feedback circuit is used for extending the bandwidth. The proposed design achieves a gain of 45.2 dBΩ with a 3 dB bandwidth of 21.23 GHz. The active feedback circuit provides an additional bandwidth of 7.3 GHz. The TIA achieves a data rate of 30 Gb/s with input‐referred noise current density of 63.1 pA/ and jitter of 9.07 ps. The TIA consumes a power of 10.3 mW with a supply voltage of 1.8 V.

Forty five nm CMOS low power multilevel active feedback transimpedance amplifier for optical receivers

PurposeRecent advancements in the domain of smart communication systems and technologies have led to the augmented developments for very large scale integrated circuit designs in electro-magnetic applications. Increasing demands for low power, compact area and superior figure of merit–oriented circuit designs are the trends of the recent research studies. Hence, to accomplish such applications intended for optical communications, the transimpedance amplifier (TIA) was designed.Design/methodology/approachIn this research work, the authors present a multi-layer active feedback structure which mainly composes a transimpedance stage and a gain stage followed by a low pass filter. This structure enables to achieve improved input impedance and superior gain. A simplified cascaded amplifier has also been designed in a hierarchical topology to improvise the noise effect further. The proposed TIA has been designed using Taiwan Semiconductor Manufacturing Company 45 nm complementary metal oxide semiconductor technology. Moreover, the thermal noise has been analyzed at −3 dB bandwidth to prove the reduction in thermal noise with increase in frequency for most of the devices used in the designed circuit.FindingsThe proposed differential TIA circuit was found to obtain the transimpedance gain of 50.1 dBO without applying any external bias current which is almost 8% improvised as compared to the conventional circuit. In addition to this, bandwidth achieved was 2.15 GHz along with only 38 W of power consumption, which is reasonably 100 times improvised in comparison of conventional circuit. Hence, the proposed differential TIA is suitable for the low power optical communications applications intended to work on low supply voltage.Originality/valueThe designed work is done by authors in university lab premises and is not copied from anywhere. To the best of the authors’ knowledge, it is 100% original.

A Low Power, Low Noise, Single-Ended to Differential TIA for Ultrasound Imaging Probes

This brief presents a low power low noise amplifier (LNA) in TSMC 0.18 μm CMOS technology for ultrasound imaging probes. The proposed LNA is based on a trans-impedance amplifier (TIA). Single-ended to differential conversion is realized using a common-gate and a common-source (CG-CS) based structure. Resistive feedback is exploited to provide a noise canceling scheme for the CS transistor. Unlike the conventional CG-CS structure that can only eliminate the noise of the CG transistor, the proposed structure eliminates the noise of both CG and CS transistors as well as the CG stage load resistor. Furthermore, by using negative feedback in the CG stage and current reuse technique in both stages, power consumption is reduced. Post-layout simulation results show a trans-impedance gain of 82 dBQ with a -3 dB bandwidth of 77 MHz, while input impedance is 731 Ω. and the equivalent input referred noise is 1.95 pA/√Hz at 5 MHz. The second harmonic distortion (HD2) is lower than -48.5 dB The circuit occupies an active area of 312 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 47 μW from a 1.2 V supply.

Co-design of a differential transimpedance amplifier and balanced photodetector for a sub-pJ/bit silicon photonics receiver.

This paper presents the design and implementation of a fully differential optical receiver, which is aimed for short reach intensity modulation and direct detection (IMDD) transceiver links. A Si-Ge balanced photodetector (PD) has been co-designed and packaged with a novel differential transimpedance amplifier (TIA). The TIA design is realized with a standard 28 nm CMOS process and operates with a standard digital supply (1V). Without using any equalization or DSP techniques, the proposed receiver can operate up to 54 Gb/s with a BER less than the KP4 limit (2.2×10-4) under an optical modulation amplitude (OMA) of -8.6 dBm, while the power efficiency has been optimized to 0.55 pJ/bit (0.98 pJ/bit if output buffer is included).

Analysis and Monolithic Implementation of Differential Transimpedance Amplifiers

We present a comparison of design trade-offs for transimpedance, sensitivity, DC voltage offset cancellation, group-delay variation (GDV), common-mode rejection, and overload for transimpedance amplifiers (TIA) based on balanced, unbalanced, and pseudodifferential topologies. The TIAs are implemented monolithically in the IHP 250-nm SiGe BiCMOS EPIC process (fT = 190 GHz). Measurement results shown here support data rates to 50 Gb/s with BER better than 10−10. The power consumption of the TIAs is 54 mW for TIA designs that approach 1 pJ/b.

A switching threshold programmable high-linearity transimpedance amplifier for OLED pixel current mismatch measurement

In this paper, we present a new switching threshold programmable transimpedance amplifier (TIA) for OLED pixel current measurement system. The TIA is composed of an inverter-based cascode amplifier that achieves DC gain of 87 dB for high linearity. To maximize the current efficiency, novel biasing scheme using series capacitor between two input transconductors is proposed so that the current efficiency of NMOS and PMOS transistors are individually maximized. In order to correct random source voltage variation, the switching threshold range is adjustable with 4-bit resolution implemented in 180 nm CMOS technology, the prototype TIA achieves 4% of current-to-voltage conversion linearity error and 23 mV of switching threshold adjustment range. The implemented differential TIA consumes 165 μW under 3.3 V when operating at 5.2 kHz.

Thermomechanical-Noise-Limited Capacitive Transduction of Encapsulated MEM Resonators

The thermomechanical motion imposes the fundamental noise limit in room-temperature resonant sensors and oscillators. Due to the inherently low sensitivity of capacitive transduction in microelectromechanical (MEM) resonators, its effects are often masked by noise in the subsequent amplifier and measurement stages. In this work, we demonstrate a capacitive transduction scheme for measuring kHz-MHz frequency MEM resonators across 1 $\mu \text{m}$ capacitive gaps with 99.8% thermomechanical-noise-limited resolution. We delineate the transimpedance gain and noise of our custom off-chip differential transimpedance amplifier setup. The thermomechanical noise spectrum can provide estimates of the resonant frequency, quality factor, and electromechanical transduction factor comparable to the commonly used driven response, without the downsides of capacitive feedthrough or nonlinearity. [2019-0115]

Ultra-Low-Noise Balanced Detectors for Optical Time-Domain Measurements

Two ultra-low-noise balanced detectors used for optical time-domain measurements are presented in this paper. Both simultaneously achieve high bandwidth and low noise that is extremely difficult to realize in commercial detectors. Two-stage amplification circuits based on transimpedance amplifiers (TIAs) were used for these detectors, with special modifications implemented for different applications. To further suppress noise, a low-noise junction field-effect transistor is connected between the photodiode and TIA to reduce the impact of amplifier leakage current in one of the detectors. Benefiting from this design, a 70-MHz sensitive detector with a gain of 3.2E5 V/W and low noise-equivalent power (NEP) density of 2.2 pW/rtHz was implemented. For another balanced detector used in higher bandwidth applications, the differential TIA circuit is used, with the detector achieving a 250-MHz bandwidth with a gain of 5E4 V/W, equivalent to NEP of 6.2 pW/rtHz. Due to the difficulty of achieving high bandwidth with low noise, we perform theoretical analysis and simulations for our designs to ensure that these two design goals are realized simultaneously. The performance of the detectors is consistent with our analysis. In addition, a simplified optical testing system was built to test and calculate the performance of the detectors in their respective applications. The results show that both detectors are well-balanced and achieve a common mode rejection ratio greater than 50 dB.

A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS

This paper presents a fully differential transimpedance amplifier (TIA) realized in a standard 65-nm CMOS process, where a novel mirrored-cascode (MC) input configuration is proposed for differential signaling, i.e., an NMOS cascode amplifier with a resistive feedback for negative output and its MC amplifier via an ac-coupling capacitor for positive output. For bandwidth extension, the third-order asymmetric transformers were carefully employed. Measured results of the proposed MC differential (MCD) TIA demonstrate 54-dB $\Omega $ transimpedance gain, 40-GHz bandwidth for 50-fF photodiode capacitance, $19.8-\text{pA}/\sqrt {\mathrm {Hz}}$ average noise current spectral density, ±10-ps group delay variation, and 55.2-mW power consumption. Eye diagrams for 32 Gb/s 215 –1 pseudo random binary sequence (PRBS) were measured with the input currents of 100–1.5 mApp. The chip occupies the area of 0.6 mm2 including I/O pads.

A 106-Gb/s PAM-4 Silicon Optical Receiver

We present a 106-Gb/s four-level pulse-amplitude modulation (PAM-4) silicon optical receiver consisting of a low-noise fully differential transimpedance amplifier (TIA) wirebonded to a high-speed silicon photonic Ge photodiode (PD). A low-noise operation is achieved through a fully differential TIA architecture, combined with active on-chip biasing for the PD. To the best of our knowledge, this is the first integrated low-power optical receiver to report (sub-)KP4-FEC bit error ratios up to 53 GBd PAM-4 without any digital signal processing or equalization to compensate the receiver. An optical modulation amplitude sensitivity of −5 dBm at 53 GBd is obtained, while consuming 160 mW (1.51 pJ/b at 53 GBd). The receiver achieves the best-reported sensitivities from 32- up to 53-GBd PAM-4, at the lowest reported power consumption.

90-Gb/s NRZ Optical Receiver in Silicon Using a Fully Differential Transimpedance Amplifier

We present the design and implementation of a 90 -Gb/s non-return-to-zero (NRZ) direct detection optical receiver that consists of a low-noise transimpedance amplifier (TIA), fabricated in a 55-nm SiGe BiCMOS technology, and a Ge photodiode integrated into a Silicon Photonic integrated circuit. Low-noise broadband operation is achieved using a fully differential TIA that provides the photodiode reverse bias. 50-, 56-, and 64-Gb/s NRZ operation is demonstrated at bit-error ratios (BERs) below $10^{-12}$ at sensitivities of $-$ 12.3-, $-$ 11.2-, and $-$ 11.1-dBm optical modulation amplitude (OMA) while consuming 128, 141, and 157 mW, respectively. Furthermore, a BER below $10^{-12}$ is achieved at 80 Gb/s with a sensitivity of $-$ 6.1 dBm (OMA) at 165 mW, and operation below KP4-FEC $({2.4 \times {10}^{-4}})$ is demonstrated up to 90 Gb/s with a sensitivity of $-$ 7.1 dBm (OMA) while consuming 222 mW. All BERs were measured in real time and without DSP or equalization to compensate the receiver. The presented receiver achieves the best reported sensitivities up to 90 Gb/s, at the second-lowest power consumption, and is the first reported integrated optical RX up to 90 Gb/s that is tested in real time without any equalization or DSP to compensate the receiver. The presented optical receiver is ideally suited for upcoming short-reach applications.

A Linear Differential Transimpedance Amplifier for 100-Gb/s Integrated Coherent Optical Fiber Receivers

This paper presents the design and measurements of a 32-Gb/s differential-input differential-output transimpedance amplifier (TIA) employed in dual polarization integrated coherent receivers for 100-Gb Ethernet. A circuit technique is shown that uses a replica TIA to stabilize the operating point of the two shunt-feedback input stages as well as to cancel the dc part of the two complementary input currents and balances their offset. The TIA can be operated in two modes, an automatic gain control mode to retain a good total harmonic distortion (THD) over a wide dynamic range and a manual gain control mode. Electrical as well as optical-electrical characterization of the TIA are presented. It achieves a maximum differential transimpedance of 74 dB $\Omega $ , 33 GHz of 3-dB bandwidth, 12.2 pA/ $\sqrt {\text {Hz}}$ of average input-referred noise current density with the photodiode, 900 mVpp of maximum differential output swing, less than 1% of THD for 600 mVpp differential output swing, and 500 $\mu \text{A}_{\text {pp}}$ differential input current. The linearity of the TIA is furthermore demonstrated with PAM4 measurements at 25 Gbaud. The dual TIA chip is fabricated in a 0.13- $\mu \text{m}$ SiGe:C BiCMOS technology, dissipates 436 mW of power and occupies 2 mm2 of area.

RF Transimpedance Amplifier for CATV Applications over PON

In this work, we present a fully differential transimpedance amplifier (TIA) with controllable transimpedance for use in RF overlay downstream communication systems. The transimpedance amplifier has been designed in a standard 180-nm CMOS technology and it is intended for 47 MHz to 870 MHz subcarrier multiplexed RF signals. It performs a 18 dBΩ transimpedance gain control range for extended optical input range from -6 dBm up to +2 dBm.

A Wide Dynamic Range CMOS Laser Radar Receiver With a Time-Domain Walk Error Compensation Scheme

This integrated receiver channel designed for a pulsed time-of-flight (TOF) laser rangefinder consists of a fully differential transimpedance amplifier channel and a timing discriminator. The amplitude-dependent timing walk error is compensated by measuring the width and rise time of the received pulse echo and using this information for calibration. The measured bandwidth, transimpedance and minimum detectable signal (SNR ~10) of the receiver channel are 230 MHz, $100~\text {k}\Omega $ and ${\sim } 1~\mu \text {A}$ respectively. The single-shot precision of the receiver is ~3 cm at an SNR of 13 and the measurement accuracy is ±4 mm with compensation within a dynamic range of ~1:100 000. The receiver circuit was realized in a $0.35~\mu \text {m}$ CMOS process and has a power consumption of 150 mW. The functionality of the receiver channel was verified over a temperature range of -20 °C to +50 °C.

Transimpedance Limit Exploration and Inductor-Less Bandwidth Extension for Designing Wideband Amplifiers

This brief studies the transimpedance of the regulated cascode (RGC) structure and develops a multilevel active feedback (MLAF) structure to build an inductorless CMOS differential transimpedance amplifier (TIA). The proposed TIA consists of an input stage, a single-to-differential circuit, a gain stage, and an output buffer. The input stage adopts the RGC structure of which transimpedance is theoretically characterized and numerically analyzed to determine design parameters. In the gain stage, the MLAF structure in a hierarchical feedback topology is investigated to increase the bandwidth without inductor peaking. The proposed differential TIA was simulated at the 180-, 90-, and 28-nm CMOS technologies to verify our design methodology. In addition, the TSMC 180-nm CMOS technology was employed to implement the proposed TIA with a core size of 0.05 mm $^{2}$ , a bandwidth of 7.2 GHz, and a differential transimpedance gain of $1.8~{\mathrm{ k}}\Omega $ . Comparing with conventional TIAs, the proposed TIA exhibits the least hardware cost and fairly good performance for applications of 10-Gbit/s optical communications.