Abstract
This paper presents the design and implementation of a fully differential optical receiver, which is aimed for short reach intensity modulation and direct detection (IMDD) transceiver links. A Si-Ge balanced photodetector (PD) has been co-designed and packaged with a novel differential transimpedance amplifier (TIA). The TIA design is realized with a standard 28 nm CMOS process and operates with a standard digital supply (1V). Without using any equalization or DSP techniques, the proposed receiver can operate up to 54 Gb/s with a BER less than the KP4 limit (2.2×10-4) under an optical modulation amplitude (OMA) of -8.6 dBm, while the power efficiency has been optimized to 0.55 pJ/bit (0.98 pJ/bit if output buffer is included).
Highlights
Global interest in developing silicon photonic interconnects to meet the growing demands for short reach communication has increased dramatically over the last decade [1]
We present the design and characterization of an optical receiver that is composed of a 28nm CMOS transimpedance amplifier (TIA) and a balanced Si-Ge photodetector
Experimental results To validate the structure and circuit topologies of the proposed differential optical receiver, the photodetector has been fabricated in the Interuniversity Microelectronics Centre (IMEC) iSiPP50G process, in which a pair of PDs, one Multimode Interference (MMI) and one grating coupler have been carefully laid out with an overall chip area of 0.17mm2
Summary
KE LI,1 * SHENGHAO LIU, XIAOKE RUAN, DAVE.J.THOMSON, YANG HONG, FAN YANG, LEI ZHANG, COSIMO LACAVA, FANFAN MENG, WEIWEI ZHANG, PERIKLIS PETROPOULOS, FAN ZHANG, GRAHAM.T.REED1. Abstract: This paper presents the design and implementation of a fully differential optical receiver, which is aimed for short reach intensity modulation and direct detection (IMDD) transceiver links. A Si-Ge balanced photodetector (PD) has been co-designed and packaged with a novel differential transimpedance amplifier (TIA). The TIA design is realized with a standard 28nm CMOS process and operates with a standard digital supply (1V). Without using any equalization or DSP techniques, the proposed receiver can operate up to 54Gb/s with a BER less than the KP4 limit (2.2×10-4) under an optical modulation amplitude (OMA) of -8.6dBm, while the power efficiency has been optimized to 0.55pJ/bit (0.98pJ/bit if output buffer is included)
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