Differential-pair Circuit Research Articles

Comparative Analysis of CNTFET Models through the Design of a Differential Amplifier

In this paper we compare simulation results on a differential pair circuit using a CNTFET model, already proposed by us, with the result obtained using Stanford model. We study the case of differential pair with differential input and single ended output as core of a 50 GHz amplifier for mm waves band. We consider the case of a CNTFET having a single CNT tube with indices (19,0) and 25 nm long. For this circuit we present result for its main parameters: gain, input impedance, output impedance, noise and distortion. Since the Stanford model includes fixed capacitance, for comparison we applied the same capacitance on our model. Since this capacitances dominate the high frequency cut, results are not much different, except for the lack of noise modelling in the Stanford model.

Design of High-Speed Quaternary D Flip-Flop Based on Multiple-valued Current-mode

A new type of quaternary D flip-flop based on multiple-valued current-mode is presented for high-speed sequential circuit in VLSI systems. It employs master-slave mode and dynamic multiple-valued source-coupled logic. A distinguishable multiple-valued interval, fast switch speed and compact structure are obtained by combining source-coupled logic with differential-pair circuit. The performance evaluation is carried out with HSPICE using 0.18μm CMOS process. A performance comparison with those issued in some references is conducted. The delay in our design is about 74% reduced by comparison with the corresponding binary implementation. The circuitry proposed is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential and feasible method of high-performance VLSI systems.

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (Ad), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest Ad, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher Ad and ON-state current than Point TFETs.

New Programmable CMOS Fuzzifier and C2V Circuits Applicable in FLC Chip for Signal Processing of MEMS Glucose Sensors

This paper presents the design and simulation of improved circuits of Fuzzifier and capacitance to voltage (C2V) converter. The Fuzzifier circuit is designed based on analog advantages such as low die area, high accuracy, and simplicity which are added to the fuzzy system advantages. For implementing this idea, a programmable Membership Function Generator (MFG) including differential pair circuit as a Fuzzifier is proposed. The MFG generates arbitrary forms of Gaussian, Trapezoidal, and Triangular shapes. The shape types are achieved using control switches and different reference voltages. This structure is also general purpose in tuning the slope of Membership Functions (MFs) using scaled transistors with different W/L ratios. With a specific purpose in mind, we used it here to generate fuzzy language terms from sensed classic data of a blood glucose microsensor. Thus we proposed a C2V circuit to convert capacitance variations (from MEMS glucose microsensor) to voltage values as classic data. The proposed mentioned circuits can be applicable in design of Fuzzy Logic Controller (FLC) chips to detect blood glucose, process its data in Fuzzy environment, and control insulin injection of diabetic patients by MEMS micropumps. The simulation results are achieved by MATLAB and Hspice software in 0.35 μm CMOS standard technology.

A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits

A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits

Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits

A fine-grain bit-serial multiple-valued reconfigurable VLSI based on logic-in-control architecture is proposed for effective use of the hardware resources. In logic-in-control architecture, the control circuits can be merged with the arithmetic/logic circuits, where the control and arithmetic/logic circuits are constructed by using one or multiple logic blocks. To implement the control circuit, only one state in a state transition diagram is allocated to one logic block, which leads to reduction of the complexity of interconnections between logic blocks. The fine-grain logic block is implemented based on multiple-valued current-mode circuit technology. In the fine-grain logic block, an arbitrary 3-variable binary function can be programmed by using one multiplexer and two universal literal circuits. Three-variable binary functions are used to implement the control circuit. Moreover, the hardware resources can be utilized to construct a bit-serial adder, because full-adder sum and carry can be realized by programming in the universal literal circuit. Therefore, the logic block can be effectively reconfigured for arithmetic/logic and control circuits. It is made clear that the hardware complexity of the control circuit in the proposed reconfigurable VLSI can be reduced in comparison with that of the control circuit based on a typically sequential circuit in the conventional FPGA and the fine-grain field-programmable VLSI reported until now.

Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit-serial reconfigurable computation is proposed. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a simple logic block can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple-valued signaling, where superposition of serial data bits and a start signal which indicates heading of one-word is introduced. Differential-pair circuits are also effectively employed for current-output replication, which leads to high-speed signaling to adjacent cells The evaluation is done based on 90 nm CMOS design rule, and it is made clear that the area of the proposed cell can be reduced to 78% in comparison with that of the CMOS implementatiuon. Moreover, its area-time product becomes 92% while the delay time is increased by 18%.

Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation

In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90nm CMOS technology is superior to those of the corresponding ordinary implementation.

Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry

This paper presents a high-speed 54 x 54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8V supply occupying a 0.85 mm 2 active area.

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic

A new static storage component, a quaternary flip-flop which consists of two-bit storage elements and three four-level voltage comparators, is proposed for a high-performance multiple-valued VLSI-processor datapath. A key circuit, a differential-pair circuit (DPC), is used to realize a high-speed multi-level voltage comparator. Since PMOS cross-coupled transistors are utilized as not only active loads of the DPC-based comparator but also parts of each storage element, the critical delay path of the proposed flip-flop can be shortened. Moreover, a dynamic logic style is also used to cut steady current paths through current sources in DPCs, which results in great reduction of its power dissipation. It is evaluated with HSPICE simulation in 0.18 μm CMOS that the power dissipations of the proposed quaternary flip-flop is reduced to 50 percent in comparison with that of a corresponding binary CMOS one.

A 80-gbit/s D-type flip-flop circuit using InP HEMT technology

80-Gbit/s operation of a static D-type flip-flop (D-FF) circuit was achieved using InP-based HEMT technology, which has a cut-off frequency of 245 GHz and a transconductance of 1500 mS/mm. The circuit was designed with differential operation based on source-coupled FET logic (SCFL). To overcome deterioration of the 80-GHz clock signals in a single-ended to differential signal converter in the input buffer, a rat-race circuit was used as a converter. Measurements showed that the circuit achieved a gain of over 2 dB higher than a conventional converter using a differential pair circuit, and power consumption was reduced from 380 to 260 mW. The power supply voltage was -5.7 V, and total power consumption was 1.2 W. Since there is no commercially available 80-Gbit/s-pulse pattern generator, we developed a selector module to measure the D-FF. These measurements showed that the D-FF successfully operated at 80 Gbit/s, which is almost twice the speed reported to date.

Differential Pair Circuit for High-Speed Intra-Chip Data Transmission

Differential Pair Circuit for High-Speed Intra-Chip Data Transmission