Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry

Abstract

This paper presents a high-speed 54 x 54-bit multiplier using fully differential-pair circuits (DPCs) in 0.18 μm CMOS. The DPC is a key component in maintaining an input signal-voltage swing of 0.2 V while providing a large current-driving capability. The combination of the DPC and the multiple-valued current-mode linear summation makes the critical path shortened and transistor counts reduced. The multiplier has an estimated multiply time of 1.88 ns with 74.2 mW at 400 MHz from a 1.8V supply occupying a 0.85 mm 2 active area.