Differential Operational Amplifier Research Articles

Design of a fully differential current mode operational amplifier with improved input–output impedances and its filter applications

In this paper, a CMOS implementation of a fully differential current-mode operational amplifier (COA) is presented. To achieve very low input resistance, a new technique based on a positive feedback is used in the input transimpedance stage. Additionally, traditional current output stage (Arbel Goldminz output stage) with improved output resistance is selected as a transconductance stage. Results of simulations exhibit 96 dB DC gain, nearly 120 Ω input, 30 M Ω output resistances and a gain-bandwidth product exceeding 90 MHz. The proposed COA is operated under ± 1.5 V voltage supplies and designed with 0.35 - μ m CMOS process. Furthermore, COA-based fourth-order band-pass (BP) filter consisting of Butterworth low-pass (LP) and high-pass (HP) filters is realized as an application example. SPICE simulation results are included to verify correctness of the designs.

A design example of a 65 nm CMOS operational amplifier

AbstractIn this paper, we discuss the properties of new nanometer‐size CMOS technologies being important for the circuit designer. Thereby we concentrate on analogue circuit design. In the literature, the gain reduction by the high output conductance of the transistors is discussed. In detail, we further describe gain reduction due to gate‐leakage current. Finally, we present a design example of a fully differential operational amplifier in a 65 nm CMOS technology including results. Copyright © 2007 John Wiley & Sons, Ltd.

1 V fully balanced differential amplifiers: Implementation and experimental results

We report a novel low voltage fully differential class AB operational amplifier and a fully balanced preamplifier, which are based on Dynamic Threshold voltage MOSFET (DTMOS) transistors. Pseudo P type DTMOS transistors are used to enhance the differential input common-mode range. The proposed circuits were fabricated using standard CMOS 0.18 μm CMOS process technology. The fully differential class AB amplifier is implemented to enhance the noise performance of low voltage high precision switched capacitor circuits, the fully balanced preamplifier is implemented to drive the differential inputs of the analog to digital converter used in the analog front-end of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. The power consumption of the proposed preamplifier is only 80 μW. The minimum experimental supply voltage is roughly 0.8 V.

A new low voltage CMOS differential OTRA for sub-micron technologies

In this study, a new CMOS differential operational transresistance amplifier (OTRA) topology is proposed. This topology can operate with a very low voltage power supply as 1.2 V. In this design, CMOS 0.13 μ m STMicroelectronics technology transistor models are used for the simulations. The designed CMOS OTRA has a transresistance gain (Rm) of 38 660 V/A with a bandwidth ( - 3 dB ) of 29.2 MHz. To demonstrate the performance of the OTRA, designed universal MOS-C filter employing two CMOS differential OTRA are tested with CADENCE simulation program to verify the theoretical results.

High frequency and high precision CMOS full-wave rectifier

This paper describes a high frequency and high precision full-wave rectifier using a fully differential input and output operational transconductance amplifier (FDIO-OTA), which is very suitable for CMOS technology implementation. The system comprises a voltage to current converter, precision full-wave rectifier and a current-to-voltage converter. An input voltage signal is converted into two symmetrical current signals by using a FDIO-OTA. Two current signals will be rectified by using MOS diodes and convert into output voltage by using grounded MOS resistor. The circuit exhibits a very precise rectifier and very high operating frequency. The simulation results demonstrate the performance of the proposed circuit.

Finite common-mode rejection in fully differential operational amplifiers

A nonlinear mechanism which affects common-mode rejection (CMR) of fully differential integrated operational amplifiers (opamps) is highlighted and analysed by computer simulations. In particular, it is shown how the finite CMR of fully differential opamp circuits under practical operating conditions is mainly related to such a mechanism rather than to transistor mismatch.

A Novel CMOS Realization of the Differential Input Balanced Output Current Operational Amplifier and its Applications

In this paper a new realization of the differential input balanced output current opamp is proposed, operating with ±1.5 V supplies. Its architecture is based on the use of current inverters to sense the input currents while providing a very low input resistance, 23 ?. The opamp provides a maximum output swing of 700 ?A, with an input offset current of 3.5 nA. The differential gain achieved is 65.5 dB, and the differential structure adopted in the design provided a high CMRR, 89.5 dB, the proposed circuit is compared to other realizations with single and differential inputs. The applications of the current opamp are exploited some new applications are presented such as: MOSFET-C integrators, full non-linearity cancellation for MOS transistors, and finally a digitally tuned current-mode variable gain amplifier, which has a gain tuning range of 25 dB with a 0.05 dB step.

Fully Differential CMOS Current Feedback Operational Amplifier

This paper presents a new CMOS fully differential current feedback operational amplifier (FDCFOA). The proposed CMOS realization of the FDCFOA is based on a novel class AB fully differential buffer...

10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다. This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

Miller Compensation Using Current Buffers in Fully Differential CMOS Two-Stage Operational Amplifiers

Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.

Low-voltage operational amplifier in 0.12 μm digital CMOS technology

A fully differential low-power operational amplifier in 0.12 μm digital CMOS technology achieving a differential gain of 80 dB is presented. A transit frequency of 20.5 MHz at ±0.7 V supply and with a load of 10 pF has been measured. Owing to an innovative bulk controller for the input transistors, the common-mode input range is larger than ±0.2 V. The operational amplifier can be used down to a supply voltage of ±0.4 V with a differential gain of 63.5 dB.

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

The authors present a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. Owing to the class AB operation in the second stage, slew limiting occurs only in the first stage, resulting in low power dissipation for switched-capacitor circuits. It employs a novel hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for the minimum settling time of the proposed OTA is described. To demonstrate the efficiency of the proposed OTA and its compensation method three design examples are also provided.

Nonlinear effects in pseudo differential OTAs with CMFB

A general description of nonlinearities in pseudo differential operational transconductance amplifiers (OTA) with common-mode feedback (CMFB) is introduced. The effects of CMFB nonlinearities on the differential signals are evaluated and design tradeoffs including nonidealities are determined. A practical pseudo differential fully balanced fully symmetric OTA architecture with common-mode feedforward (CMFF) is used as a case study to probe the theory. The OTA has an inherent common-mode detector; hence, the CMFB circuit is efficiently implemented. The OTA is used to implement a 100-MHz fourth-order linear-phase OTA-C filter.

Compact sub-hertz ota-c filter design with interface-trap charge pump

Single-ended and differential operational transconductance amplifier (OTA) configurations are biased with MOSFET interface-trap charge-pumping (ITCP) current generators to achieve very low transconductances for tunable sub-hertz operational transconductance amplifier-capacitor (OTA-C) filter implementation. This paper reviews the basics of ITCP current generation and presents the transconductors and the OTA-C filter configurations based on these transconductors. One of the filters is a low-pass with an experimentally determined lowest cutoff frequency of 0.18 Hz, and the other is a fully differential bandpass with individually tunable lower and upper cutoff frequencies measured down to 0.3 Hz. The former has one 15-pF filter capacitor, and measures 0.0346 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , whereas the latter contains four such capacitors and occupies 0.188 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon. Experimental evaluation also includes offset, harmonic distortion, and noise performance.

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of VDD=1.5 V, using a 0.6 µm CMOS technology with transistor threshold voltages of VTN=0.75 V and VTP=−0.85 V. Post-layout simulation results for a load capacitance (CL) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 µW.

Low-power low-voltage differential class-AB OTAs for SC circuits

Two new differential class-AB operational transconductance amplifiers (OTAs) for SC circuits that operate with a supply voltage of less than two transistor threshold voltages are introduced. They make use of a new class-AB pseudodifferential pair to generate signal currents much larger than quiescent currents. Both OTAs have been designed to operate with a supply voltage of V/sub DD/=1.1 V, using a 0.35 /spl mu/m CMOS technology. Simulation results for a load capacitance (C/sub L/) of 1 pF show 15 MHz gain-bandwidth product with a quiescent power consumption of 10 /spl mu/W.

High-frequency two-input CMOS OTA for continuous-time filter applications

A high-frequency fully differential CMOS operational transconductance amplifier (OTA) is presented for continuous-time filter applications in the megahertz range. The proposed design technique combines a linear cross-coupled quad input stage with an enhanced folded-cascode circuit to increase the output resistance of the amplifier. SPICE simulations show that DC-gain enhancement can be obtained without significant bandwidth limitation. The two-input OTA developed is used in high-frequency tuneable filter design based on IFLF and LC ladder simulation structures. Simulated results of parameters and characteristics of the OTA and filters in a standard 1.2 /spl mu/m CMOS process (MOSIS) are presented. A tuning circuit is also discussed.

Symmetrically compensated fully differential folded-cascodeOTA

A symmetric compensation technique that improves the phase response for fully differential folded-cascode operational transconductance amplifiers (OTA) is proposed. Theory and simulated results show that the magnitude response and settling time for symmetrically compensated OTAs are also improved in comparison with those of compensated and typical OTAs.

Non-stationary noise responses of some fully differential on-chip readout circuits suitable for CMOS image sensors

CMOS active-pixel image sensors, as well as charge-coupled devices, generate both white noise and 1/f/sup /spl alpha//-noise over several decades depending on biasing current, operating temperature, and the characteristics of the process used, limiting the detector dynamic range. Three readout circuits, based on a fully differential cascode operational transconductance amplifier, designed and realized on a standard CMOS 0.7-/spl mu/m single polysilicon/double metal process, are proposed for CMOS active-pixel imagers. The first is an uncompensated switched capacitor (SC) voltage amplifier; the second, an offset compensated SC amplifier; and the third, a commutable bandpass filter. All three amplifiers allow correlated double sampling and double delta sampling for pixel and column fixed pattern noise suppression, respectively. The amplifiers offer up to 10-Mpixels/s readout rates. A detailed theoretical analysis of the amplifiers response to white noise and low-frequency excess noise is given, considering nonstationary nature of the output signals. An original method based on diffusive Markovian representation of 1/f/sup /spl alpha//-noise is used. The theoretical results are compared with experimental data.

A 12-bit medium-time analog storage device in a CMOS standard process

A new 12-bit medium-time analog storage device is presented. The proposed circuit is based on a fully differential two-stage operational amplifier (opamp) working as a sample-and-hold circuit (S&H). A novel refresh scheme employing common-mode rejection has been developed which extends the storage time on a capacitance beyond the border of voltage decay caused by charge leaking. Measurements show 12- and 8-bit resolution for 15 and 330 s, respectively, at room temperature. Compared to analog storage on a simple capacitance, the new scheme offers 84% area reduction for the same storage times while achieving much faster read-write cycle times. The circuit is intended for use in analog neural networks. The basic idea can be extended to design simple low-cost S&H circuits.