Differential Operational Amplifier Research Articles

0.5 V Multiple-Input Fully Differential Operational Transconductance Amplifier and Its Application to a Fifth-Order Chebyshev Low-Pass Filter for Bio-Signal Processing.

This paper presents a multiple-input fully differential operational transconductance amplifier (MI-FD OTA) with very low power consumption. To obtain a differential MOS pair with minimum supply voltage and minimum power consumption, the multiple-input bulk-driven MOS transistor operating in the subthreshold region is used. To show the advantage of the MI-FD OTA, a fifth-order Chebyshev filter was used to realize a low-pass filter capable of operating with a supply voltage of 0.5 V and consuming 60 nW at a nominal setup current of 3 nA. The proposed filter uses five MI-FD OTAs and five capacitors. The total harmonic distortion (THD) was 0.97% for a rail-to-rail sinusoidal input signal. The MI-FD OTA and the filter application were designed and simulated in the Cadence environment using a 0.18 µm CMOS process from TSMC. The robustness of the design was confirmed by Monte Carlo analysis and process, voltage, and temperature corner analysis.

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

Abstract: Operational amplifier circuits are used in computation, instrumentation and other applications. Precision op-amps previously used in instrumentation are now-a-days being used in industrial and automotive applications. Hence, there always exists a need for better precision op-amps. It should operate under a wide temperature range. Nowadays, due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip, Complementary Metal-Oxide Semiconductor (CMOS) technology has become dominant over bipolar technology for analog circuit design in a mixed-signal system. Two-stage Op-Amp is one of the most commonly used Op-Amp architectures. In this work an operational amplifier based on CMOS is presented whose input depends on its bias currents which is 20µA and designed using 180nm and 90nm technologies. In sub-threshold region due to unique behavior of the MOS transistors not only allows a designer to work at low voltages and it also allows operating at low input bias currents. Most CMOS Op-Amps are designed for specific on-chip applications and are only required to drive capacitive loads of a few pf. In this proposed work, design of a two stage fully differential CMOS operational amplifier is presented and simulations are carried out in 180nm and 90nm technologies for various parameters. The simulation is to be carried out using Cadence Virtuoso Tool.

A design of fully differential operational amplifier for switched-capacitor application

Switched-capacitor (SC) circuit is used widely in communication and signal processing systems, such as switched-capacitor filter and switched-capacitor integrator. This paper proposes a fully differential operational amplifier for switched-capacitor application. The designed amplifier comprises common mode feedback circuit, auxiliary amplifier and main amplifier using fold cascode structure and its biasing circuit. The supply voltage VDD is 1V and VSS is -1V. After the simulation using TSMC 0.18μm process model, the simulation result shows the proposed amplifier achieve about 100.6dB DC gain, 66 degree phase margin,333 MHz unit gain bandwidth, 3.78V differential output swing, 287V/μs slew rate,122.8 dB DC PSRR, 114 dB DC CMRR, 1.6mW power consumption, the input reference noise is about 6nV/√Hz at 1MHz, the Total Harmonic Distortion of this amplifier is less than about 1.05%.The proposed fully differential operation amplifier meet all the specification, and it can be used in some SC circuit applications.

A 0.8 V, 14.76 nVrms, Multiplexer-Based AFE for Wearable Devices Using 45 nm CMOS Techniques.

Wearable medical devices (WMDs) that continuously monitor health conditions enable people to stay healthy in everyday situations. A wristband is a monitoring format that can measure bioelectric signals. The main part of a wearable device is its analog front end (AFE). Wearables have issues such as low reliability, high power consumption, and large size. A conventional AFE device uses more analog-to-digital converters, amplifiers, and filters for individual electrodes. Our proposed MUX-based AFE design requires fewer components than a conventional AFE device, reducing power consumption and area. It includes a single-ended differential feedback operational transconductance amplifier (OTA) and n-pass MUX-based AFE circuits which are related to the emergence of low power, low area, and low cost AFE-integrated chips that are required for wearable biomedical applications. The proposed 6T n-pass multiplexer measures a gain of -68 dB across a frequency range of 100 kHz with a 136.5 nW power consumption and a delay of 0.07 ns. The design layout area is approximately 9.8 µm2 and uses 45 nm complementary metal oxide semiconductor (CMOS) technology. Additionally, the proposed single-ended differential OTA has an obtained input referred noise of 0.014 µVrms, and a gain of -5.5 dB, while the design layout area is about 2 µm2 and was designed with the help of the Cadence Virtuoso layout design tool.

Hybrid Inverter-Based Fully Differential Operational Transconductance Amplifiers

Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations.

Notch filter on differential difference operational amplifier

A new notch filter (NF) circuit based on a single differential difference operational amplifier (DDA) has been developed and studied, which is characterized by reduced current consumption in the static mode. Equations are obtained for the transfer functions and parameters of the NF, which includes a low-pass filter and a Sallen-Key high-pass filter, the signals of which are summed by the DDA. Computer modeling of the NF in CAD Micro-Cap was performed.

Cryogenic front-end amplifier design for large SiPM arrays in the DUNE FD1-HD photon detection system

The photon detection system of the first far detector (FD1-HD) of the DUNE experiment will detect scintillation photons produced by particle interactions in a kiloton-scale liquid Argon time projection chamber. The photon detectors of choice are silicon photomultipliers (SiPM), 6×6 mm2 each, arranged in groups of 48, which present a significantly low impedance to the front-end electronics. This paper details the design of a cryogenic amplifier with exceptionally low white voltage noise of 0.37 nV√(Hz), based on a silicon-germanium input transistor and a BiCMOS fully differential operational amplifier. It yields excellent single photoelectron resolution even at low overvoltage values. The signal rise time is below 100 ns, and the dynamic range is about 2000 photoelectrons at the typical operating overvoltage. It draws 0.7 mA from a single 3.3 V supply, for a power consumption of 2.4 mW per channel. Simplified models were developed to predict the single photolectron signal shape and the signal to noise ratio, with a good match to measured performance.

A 3.95 ppm/°C 7.5 μW Second-Order Curvature Compensated Bandgap Reference in 0.11 μm CMOS

In order to meet the requirements of modern portable electronics for high accuracy and low power consumption of bandgap reference circuits, a new low-voltage bandgap reference with a second-order compensated circuit at 1.8 V is proposed. It features a new self-biased fully symmetric differential operational amplifier circuit with the help of split transistors for achieving low power consumption and high accuracy; by adding a new sub-threshold compensated circuit. The results of simulation show that the temperature coefficient of the second-order circuit is 3.95 ppm/°C in the temperature range of −40 to 125 °C, and the power consumption is only 7.5 μW; this meets both the requirements of high precision and low power consumption. At the same time, the output noise voltage of the design is less than 30 μV/sqrt (Hz) at a frequency of 100 Hz, and the low-frequency supply voltage rejection ratio is −103 dB@100 Hz; these are acceptable for bandgap reference circuits.

A Reference Source Circuit Design for Voltage Controlled Oscillator Chips

The basic principle and typical structure of the bandgap voltage reference source are introduced in detail in this paper. The performance index of the bandgap voltage reference is analyzed. The core circuit of a bandgap voltage reference source with good temperature characteristics and a high power supply rejection ratio (PSRR) is designed, in which a two-stage differential operational amplifier with a buffer stage is used, a start-up circuit without a capacitor is used to reduce the start-up time, and a common beta multiplication self-bias circuit is used to attenuate the effects of the power supply voltage. It is shown from the final HSPICE simulation results that the reference voltage temperature coefficient is approximately 7 ppm/°C within the range of -20 to 80°C in temperature, and the average PSRR can reach more than −56 dB within the range of 1 Hz to 10 kHz in frequency.

FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition

This article presents a method to automatically synthesize the structure and initial sizing of an operational amplifier. It is positioned between approaches with fixed design plans and a small search space of structures and approaches with generic structural production rules and a large search space with technically impractical structures. The presented approach develops a hierarchical composition graph based on functional blocks that spans a search space of thousands of technically meaningful structure variants for single-output, fully differential, and complementary operational amplifiers. The search algorithm is a combined heuristic and enumerative process. The evaluation is based on circuit sizing with a library of behavioral equations of functional blocks. Formalizing the knowledge of functional blocks in op-amps for structural synthesis and sizing inherently reduces the search space and lessens the number of created topologies not fulfilling the specifications. Experimental results for the three op-amp classes are presented. An outlook how this method can be extended to multi-stage op-amps is given.

Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application

In this work, low-voltage high-performance, fully differential current mirror Operational Transconductance Amplifiers (OTAs) are designed using DTMOS and asymmetric threshold voltage self cascode structure. Additionally cross drain coupled positive feedback and auxiliary slew-rate enhancement (SRE) technique are employed to improve the gain and slew-rate of proposed circuits. The proposed-I OTA (OTA-1) utilizes the dynamic threshold metal oxide semiconductor (DTMOS) technique which operates at low supply voltage and provides enhanced performance. However, the asymmetric threshold voltage self cascode structure used in proposed-II OTA (OTA-2) further improves the gain and other parameters. The proposed OTAs operate at ± 0.4 V dual power supply. The open-loop gain for the OTA-1 and OTA-2 is obtained as 73 dB and 82 dB with 10.04 μW and 10.77 μW power consumption, respectively. It offers enhanced slew-rate and improved GBW than the conventional OTA. Moreover, it gives high CMRR as 216 dB and 250 dB for the OTA-1 and OTA-2 respectively. The universal biquad voltage-mode filter has been realized using proposed OTAs. All simulations are performed using Mentor Graphics Eldo simulation tool with TSMC 0.18 μm process parameters. To validate the robustness of proposed OTAs, Monte Carlo analysis and corner analysis have been performed.

Improved loop stability approach in fully differential operational transconductance amplifier with common‐mode feedback circuit

AbstractThis paper proposes a new approach to improve loop stability in a typical common‐mode feedback (CMFB) circuit of a differential operational transconductance amplifier (OTA). In this paper, a differential difference amplifier (DDA) with a current mirror load is employed as a CMFB circuit. The new approach is based on using two series diode‐connected transistors operating in subthreshold region in parallel with current mirror load. The proposed approach provides a reliable good function with no reduction in the OTA performance and dynamic operation of CMFB loop. The proposed scheme attains necessary high gain and large bandwidth with required phase margin for CMFB circuit. The proposed CMFB circuit is employed in a typical OTA structure. The post‐layout simulation results in TSMC 130‐nm CMOS technology show that the proposed approach leads to a better phase margin of 80°, a high unity gain bandwidth of 800 MHz, and a loop gain of 27 dB for the CMFB circuit.

Positive-Feedback-Based Design Technique for Inherently Stable Active Load Toward High-Gain Amplifiers With Unipolar a-IGZO TFT Devices

This letter presents analysis of an inherently stable positive-feedback-based active load, first reported in our prior work, to realize high gain analog amplifiers using unipolar a-IGZO TFT technology. Additionally reported are theoretical performance bounds and design guidelines to maximally utilize a general positive-feedback scheme for the active load while maintaining stability. To demonstrate a design implementation, a single stage fully differential operational transconductance amplifier with common mode feedback has been manufactured and measured to have 40-dB open-loop gain at dc and a unity gain frequency of 61 kHz while driving a 30-pF load capacitance.

A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

A 0.25-V 90 dB PVT-stabilized four-stage OTA with linear Q-factor modulation and fast slew-rate enhancement for ultra-low supply ADCs

A high gain and stability, four-stage OTA with a linear transistor Q-factor modulation compensation (TQM) and a fast, power-constrained slew-rate enhancement (PC-SRE) is proposed for ADCs working under ultra-low supply voltage. A rail-to-rail input & output bulk-driven fully differential four-stage operational amplifier with proposed structure is also presented under 0.25 V supply voltage. By using proposed structure, the response speed and stability of designed four-stage amplifier have been greatly improved. The effectiveness of the circuit has been verified in standard 65 nm CMOS process, the proposed three-stage amplifier has 90.9 dB DC-gain, 31.2 kHz unity-gain frequency, and 78.2° phase margin while consuming 32.8nW power, and occupying chip area of 0.00082 mm2 from a 0.25 V supply while driving a 100pF load.

Active Charge Balancer With Adaptive 3.3 V to 38 V Supply Compliance for Neural Stimulators

Charge balancing has become a common key safety requirement of electrical stimulation systems. It reduces the risk of electrode dissolution and tissue damage, which might arise after unbalanced stimulation pulses. A CMOS integrated consequence-based active charge balancer is presented that instantaneously removes excess charges between two consecutive stimulation pulses. This balancer provides a highly adaptive power supply compliance from 3.3 V to 38 V, verified by measurements. In order to maintain the compensation behavior and efficacy over the entire supply range and to protect the active components at such high voltages, a quad-rail design is elaborated that overcomes the technological high voltage limitations of the employed 0.35 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The presented charge balancing circuit consists of a fully differential operational transconductance amplifier for monitoring and voltage level translation, as well as an advanced class-B stage as current driver, designed in accordance with the quad-rail concept. Further system flexibility is provided by incorporating three different compensation current limitations of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 500~\mu \text{A}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 300~\mu \text{A}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm 200~\mu \text{A}$ </tex-math></inline-formula> . Additionally, two safety limits of ±50 mV and ±100 mV have been adopted. The charge balancer is very power efficient, it only dissipates 6.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> and 25 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> , at 3.3 V and 38 V respectively.

Design and simulation of high-swing fully differential telescopic Op-Amp

This article describes the process of design and simulation of a high-swing fully differential telescopic operational amplifier (Op-Amp). Due to the common gate-common source (CG and CS) cascode structure, the gain is very high. To maximize this gain, the load must also be selected such as two current sources. This circuit has the higher voltage in output than current Op-Amps in accordance with desirable characteristics. The loss of power of this operating amplifier are very low and in milliwatts. With use of a power supply of 1.8 V, it achieves a high-swing 1.2 V, a differential gain of 76.333 dB, ωuGB of 412 MHz, and &gt;50 dB CMRR. This new design through the simulations and analytically shows that the high-swing fully differential telescopic Op-Amp retains its high CMRR even at high frequencies.

Design and simulation of high-swing fully differential telescopic Op-Amp

This article describes the process of design and simulation of a high-swing fully differential telescopic Operational Amplifier (Op-Amp). Due to the Common Gate-Common Source (CG and CS) cascode structure, the gain is very high. To maximize this gain, the load must also be selected such as two current sources. This circuit has the higher voltage in output than current Op-Amps in accordance with desirable characteristics. The loss of power of this operating amplifier are very low and in milliwatts. With use of a power supply of 1.8 V, it achieves a high-swing 1.2 V, a differential gain of 76.333 dB, ω_uGB of 412 MHz, and 50 dB CMRR. This new design through the simulations and analytically shows that the high-swing fully differential telescopic Op-Amp retains its high CMRR even at high frequencies.

Low‐offset differential output switched‐capacitor interface for micro‐capacitive acceleration sensors

This paper presents two simple but effective switched capacitor based differential output capacitive sensor interfaces, designed and fabricated in United Microelectronics Corporation 180 nm complementary metal oxide semiconductor (CMOS) process technology. The first configuration combines chopper modulation and switched capacitor based correlated double sampling, while the second configuration utilises chopper modulation with a modified demodulation scheme to reduce noise and offset. The proposed designs utilise a fully differential operational amplifier (op-amp) with single-feedback loop, which reduces the mismatch between the single-ended outputs in the differential configuration. The proposed configurations are analysed in perspective of noise to achieve high accuracy with less noise and integrated with supporting circuitry. The fabricated application specific integrated circuit (ASIC) is first characterised with the internal on-chip capacitors and then integrated with micro-electro-mechanical systems (MEMS) based differential capacitive accelerometer sensor on a printed circuit board (PCB) for dynamic testing. The integrated PCB and a commercially available accelerometer (ADXL335) is mounted on a sub-woofer system and the dynamic testing is carried out. The measurement results show that the sensor interface is capable of measuring sub-fF capacitance change with zero offset less than 2 mV. The first configuration provides sensitivity of 720 mV/g, whereas the second configuration attains sensitivity of 385 mV/g. The noise floors are 400 μ g / Hz , 325 μ g / Hz , whereas the capacitance resolutions are 70 and 60 aF, respectively.

A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications

A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm2 from a 0.3 V supply while driving a 100pF load.