Differential Opamp Research Articles

Efficient kernel functions for support vector machine regression model for analog circuits’ performance evaluation

Support vector machines (SVMs) have been widely used for creating fast and efficient performance macro-models for quickly predicting the performance parameters of analog circuits. These models have proved to be not only effective and fast but accurate also while predicting the performance. A kernel function is an integral part of SVM to obtain an optimized and accurate model. There is no formal way to decide, which kernel function is suited to a class of regression problem. While most commonly used kernels are radial basis function, polynomial, spline, multilayer perceptron; we have explored many other un-conventional kernel functions and report their efficacy and computational efficiency in this paper. These kernel functions are used with SVM regression models and these macromodels are tested on different analog circuits to check for their robustness and performance. We have used HSPICE for generating the set of learning data. Least Square SVM toolbox along with MATLAB was used for regression. The models which contained modified compositions of kernels were found to be more accurate and thus have lower root mean square error than those containing standard kernels. We have used different CMOS circuits varying in size and complexity as test vehicles--two-stage op amp, cascode op amp, comparator, differential op amp and voltage controlled oscillator.

Fully differential leapfrog implementation for high-pass ladder filters

This paper presents a novel leapfrog signal flow graph (SFG) implementation by fully differential Op amp integrators, which combines low sensitivity, high dynamic range with simple circuit configuration. The direct SFG simulation and leapfrog SFG simulation can yield integrator-based structures likewise, but both of them will lead to higher circuit complexity, noise density and sensitivity. Three Butterworth 5-order high-pass filters with a pass band edge frequency of 1.778 kHz are designed based on different SFGs. From the example, the noise density of the simplest leapfrog configuration is approximately 0.4 nV/Hz1/2 lower than those of the other two in the stop band, and shows the best noise density in the pass band. The sensitivity densities of two types of leapfrog filters are approximately equivalent, while that of the direct SFG simulation filter is much higher. However, the pass band response of the simplest configuration is not as good as those of the other two because of two parasitic zeros (at 708 kHz, −31.6 dB and 1.59 MHz, −20.55 dB) and a parasitic pole (at 4.57 MHz, 45.5 dB).

Triple wavelength LED driver for optical brain–computer interfaces

A dedicated triple wavelength LED driver is presented for optical brain–computer interfacing (BCI). The solution caters for the constraints of a common-anode grounded case and modulation up to several kilohertz that allows source separation of light that has backscattered from the brain. With total harmonic distortion of 0.95% and a frequency range of ~40 kHz, the driver has application in a continuous wave optical BCI. Other modulation strategies such as time division multiplexing (TDM) are catered for, owing to input DC coupling. Linearity in the optical output is maintained by the ‘load sensing’ differential op-amp on the LED’s current limiting resistor, which is the basis for the V-I conversion.

IEEE Technology Management Council

There are other non-idealities that have not been modeled here. The gain of the fully differential op amp is dependent on its voltage output. The sampling switches inject charge non-linearly as a function of the input voltage. Both of these non-idealities create harmonic distortion in the modulator output. These have been left out of the model because they do not strongly determine the integrator power. The effect of switch resistance on settling has not been modeled, but including it may show that more op amp power is needed to compensate for the modest increase in the settling time constant. Conclusions This paper demonstrates that a behavioral model, which models charge sharing, slewing, settling, and total thermal noise, can be used to optimize the power of a SC integrator employing a single stage, class A op amp. Information gained from such an optimization can be used to decide whether a different modulator architecture or more complex op amp is needed, or it can be used determine the number of quantizer levels needed in a multibit modulator. Once the power has been optimized, the designer can use the optimization result as a baseline to design the integrator with real devices, discovering where additional power may be needed to accommodate other non-idealities that were not addressed.

The universal opamp and applications in continuous-time resistorless and capacitorless linear weighted voltage addition

A versatile analog building block denoted the universal operational amplifier (opamp) is introduced. The circuit is a generalized version of the fully differential difference opamp with 2n weighted differential inputs. Applications in resistorless and capacitorless continuous-time linear weighted voltage addition are discussed. Experimental results of a test chip prototype are shown that validate the proposed approach. Simulations show potential for high frequency operation of the circuit with gain-bandwidth close to 140 MHz in 0.5-/spl mu/m CMOS technology.

New low-voltage class AB/AB CMOS op amp with rail-to-rail input/output swing

A new low-voltage CMOS Class AB/AB fully differential opamp with rail-to-rail input/output swing and supply voltage lower than two V/sub GS/ drops is presented. The scheme is based on combining floating-gate transistors and Class AB input and output stages. The op amp is characterized by low static power consumption and enhanced slew-rate. Moreover the proposed opamp does not suffer from typical reliability problems related to initial charge trapped in the floating-gate devices. Simulation and experimental results in 0.5-/spl mu/m CMOS technology verify the scheme operating with /spl plusmn/0.9-V supplies and close to rail-to-rail input and output swing.

Finite common-mode rejection in fully differential operational amplifiers

A nonlinear mechanism which affects common-mode rejection (CMR) of fully differential integrated operational amplifiers (opamps) is highlighted and analysed by computer simulations. In particular, it is shown how the finite CMR of fully differential opamp circuits under practical operating conditions is mainly related to such a mechanism rather than to transistor mismatch.

A Novel CMOS Realization of the Differential Input Balanced Output Current Operational Amplifier and its Applications

In this paper a new realization of the differential input balanced output current opamp is proposed, operating with ±1.5 V supplies. Its architecture is based on the use of current inverters to sense the input currents while providing a very low input resistance, 23 ?. The opamp provides a maximum output swing of 700 ?A, with an input offset current of 3.5 nA. The differential gain achieved is 65.5 dB, and the differential structure adopted in the design provided a high CMRR, 89.5 dB, the proposed circuit is compared to other realizations with single and differential inputs. The applications of the current opamp are exploited some new applications are presented such as: MOSFET-C integrators, full non-linearity cancellation for MOS transistors, and finally a digitally tuned current-mode variable gain amplifier, which has a gain tuning range of 25 dB with a 0.05 dB step.

A magnetic field-induced current-modulating opamp based on CMOS differential Tesla–Volt multiplier cell for MAGFET 1/ f noise reduction

A magnetic field-induced current-modulating opamp (MCMOP) based on the CMOS differential Tesla–Volt multiplier (TVM) cell for magnetic field-effect transistor (MAGFET) 1/ f noise reduction is reported. It consists of a CMOS differential TVM cell made of a pair of identical MAGFETs, a fully differential opamp, and a set of chopper-stabilization switches. Due to the modulation effect of the input voltage on the magnetic field-induced current imbalance, the MCMOP is utilized as a linear magnetic sensor not only to amplify the magnetic signal, but also to chop and stabilize the signal, so as to suppress the low frequency noise in the MAGFETs themselves. By introducing the MCMOP, the magnetic noise level of the magneto-opamp (MOP) consisting of the same differential opamp and the same single MAGFET is reduced from 160 to 25 μT/Hz 1/2 at 1 Hz. This is a 16 dB improvement of the magnetic resolution.

A CMOS Rail-to-Rail 1.5-Volt Fully Differential Opamp

The CMOS rail-to-rail fully differential Opamp has an input stage and a class AB output stage, which can provide both input and output rail-to-rail operations. Its input stage is composed of an NMOS differential pair and a PMOS differential pair. HSPICE simulation results are preformed using level 49 model of a 0.5μm CMOS process. This Opamp has a dc gain of66dB, a unity-gain bandwidth of 2.1MHz and a phase margin of 64°.

A common mode feedback structure for differential OpAmps using NMOS depletion transistors

A fully differential amplifier featuring a novel common mode feedback (CMFB) structure is presented. Measurement results for the circuit made in a 0.8 μm process prove that the new structure provides rail-to-rail common and differential mode input range that is difficult to handle for all active CMFB structures reported so far. This improvement is accomplished by the use of a nMOS depletion input pair transistors that can easily be processed in standard CMOS technologies. The differential OpAmp is designed for 3 V power supply and provides 61 dB amplification and a bandwidth of 24 MHz.

Active biasing of multistage CMOS op-amps for performance enhancement

The technique of active biasing is introduced and applied to a high-gain fully differential two-stage CMOS cascode op-amp, in order to enhance its various performance metrics such as gain, unity gain frequency, common mode and power supply rejection ratios, slew rate and settling time. The improved performance is predicted theoretically and substantiated through circuit simulations.

The differential difference operational floating amplifier: a new block for analog signal processing in MOS technology

A wide-range differential difference operational floating amplifier (DDOFA) is introduced. The DDOFA is a new block useful for continuous-time analog signal processing. The DDOFA is realized using a differential difference transconductor with large signal handling capability and a single input differential output current op-amp. The DDOFA forces two differential voltages to the same value and provides two balanced output currents. This brief presents a CMOS realization of the DDOFA, and some of its applications are provided, such as a voltage-to-current converter, MOS-grounded and floating resistors, a MOS multiplier/divider cell, a differential integrator, a continuous-time MOS-C filter, a MOS-C current oscillator, and a MOS-C floating inductor. Simulation results for the DDOFA circuit and its applications are given.

Cellular neural networks: Theory and circuit design

AbstractCellular neural networks or CNNs are a novel neural network architecture introduced by Chua and Yang which is very general and flexible, has some important properties desirable for design applications and can be efficiently implemented on custom hardware based on analogue VLSI technology.In this paper an abstract normalized definition of cellular neural networks with arbitrary interconnection topology is given. Instead of stability, the property of convergence is found to be of central importance: large classes of convergent CNNs in practice always asymptotically approach some stable equilibrium where each component of the corresponding output is binary‐valued.A highly efficient CMOS‐compatible CNN circuit architecture is then presented where a basic cell consists of only two fully differential op amps, two capacitors and several MOSFETs, while a variable interconnection weight is realized with only four MOSFETs. Since all these elements are standard components in the current analogue IC technology and since all network functions are implemented directly on the device level, this architecture promises high cell and interconnection densities and extremely high operating speeds.

An enhanced fully differential folded-cascode op amp

An enhanced fully differential folded-cascode operational-amplifier topology that achieves improved DC gain and common-mode rejection without sacrificing slew rate is presented. The large-signal operation of the new topology is completely symmetric, providing equal positive and negative slew-rate behavior by making use of current mirrors rather than current sources as normally found in full differential folded-cascode op-amps. An additional advantage of the enhanced topology is that its common-mode output impedance is a factor of g/sub m/r/sub o/ (typically 1-2 orders of magnitude) lower than the differential-mode output impedance, significantly improving the common-mode rejection ratio. The predicted performance is verified by simulations and preliminary experimental results.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A low-output-impedance fully differential op amp with large output swing and continuous-time common-mode feedback

A fully differential (zero common-mode voltage) op amp has been developed which has low output impedance, but unlike source-follower output stages, it has a large output swing, namely, 8 V/sub p-p/ for 1-k Omega load and a 5-V supply. The output stage, which is a combination of common-source and source-follower stages, is driven by the two complimentary outputs of the differential-output input stage. A continuous-time common-mode feedback circuit has been used, which due to the op amp's low output impedance, causes negligible open-loop gain (95 dB) degradation. Floating compensation capacitors are used in order to reduce the capacitance value and, hence, the area (490 mil/sup 2/). >

A switched differential op-amp with low offset and reduced 1/f noise

Fully differential techniques are becoming a popular method to alleviate the problem of low dynamic range in an analog VLSI environment. Low-frequency (1/f) noise contributions and input offset voltage remain, however, as two inherent difficulties in MOS analog designs. In this paper, a dynamic technique for implementing low-noise low-offset differential op-amps by time-sharing conventional single-ended output op-amps is introduced. A differential op-amp (DOA) implemented using this technique requires relatively little redesign effort, provides both positive and negative differential inputs, and demonstrates significant reduction in 1/f noise and input offset voltage over its single-ended counterpart. The op-amp is applicable in many sampled-data networks, such as in the design of SC filters, and can be easily interfaced with existing single-ended or differential networks.

New clock feedthrough cancellation technique for analogue MOS switched-capacitor circuits

A new technique for minimising DC offsets caused by clock feedthrough in switched-capacitor circuits is presented. Unlike some techniques presented in the past, the clock feedthrough cancellation is dependent only on matching and the common mode rejection ratio of the op-amps. The technique is quite general and can be applied to most switched-capacitor circuits that use differential input op-amps.