Differential Nonlinearity Research Articles

Low-Power CMOS Laser Doppler Imaging Using Non-CDS Pixel Readout and 13.6-bit SAR ADC.

Laser Doppler imaging (LDI) measures particle flows such as blood perfusion by sensing their Doppler shift. This paper is the first of its kind in analyzing the effect of circuit noise on LDI precision which is distinctively different from conventional imaging. Based on this result, it presents a non-correlated-double-sampling (non-CDS) pixel readout scheme along with a high-resolution successive-approximation-register (SAR) analog-to-digital-converter (ADC) with 13.6b effective resolution (ER). Measurement results from the prototype chip in 0.18 μm technology confirm the theoretical analysis and show that the two techniques improve LDI sensing precision by 6.9 dB and 4.4 dB (compared to a 10b ADC) respectively without analog pre-amplification. The sensor's ADC occupies 518 μm×84 μm and is suitable for fast column parallel readout. Its differential non-linearity (DNL), integral non-linearity (INL), and input referred noise are +3.0/-2.8 LSB, +24/-17 LSB, and 110 μVrms respectively, leading to a Figure-of-Merit (FoM) of 23 fJ/state which makes it one of the most energy efficient image sensor ADCs and an order of magnitude better than the best reported LDI system using commercial high-speed image sensors.

In-house development of an FPGA-based MCA8K for gamma-ray spectrometer.

The objective of this work is domestic development of electronics instruments. It used for measuring ionization radiation and practical training at Nuclear Research Institute (NRI), Dalat, Vietnam. The aim of this work is to study and develop a novel MCA8k for Gamma-ray spectrometer concerning experimental nuclear physics. An approach for design and construction of the aforementioned instrument is to apply logic integrating techniques via Field Programmable Gate Arrays (FPGA) under Max + PlusII, Altera. The instrument allows interfacing to PC with self-developed application software. Scientific significance of this work is partly to contribute to opening a research direction in the field of nuclear electronics science for design and construction of radiation measurement instruments with the advanced IC technology in Vietnam. Practical significance of this work is partly to contribute to enhancement of capabilities in developing radiation measurement instruments for experimental research as well as practical training in nuclear physics. The advantages of FPGA: overcoming ballistic deficit, decrement of serial and parallel noise, flexible in programming, control of the system by software without an interfere of hardware. The disadvantages of FPGA: requirement of good knowledge of VHDL and professional tools for development of a expected project. A new electronics module of MCA8k has been achieved. Some main results obtained from the experimental testing are as follows: differential nonlinearity (DNL) of FPGA-MCA8k approximately 1.27%, integral nonlinearity (INL) = 0.607%, time conversion ≈ 2.2 μs, deadtime (DT) is 0.75%. Data Acquisition Program MCANRI written in VC + +6.0, self-executed under Windows XP environment.

A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490μm×7.4μm and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18 μm technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs.

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

A 10-Bit, 12 ps Resolution CMOS Time-to-Digital Converter Dedicated to Ultra-Fast Optical Timing Applications

This paper reports the design of a 10-bit, high-resolution time-to-digital converter (TDC) based on Vernier residues amplification which is a novelty. This TDC architecture allows the measurement of wide time intervals with high picosecond-range resolution. The key benefits of the proposed TDC are that it reduces conversion jitter and provides more design flexibility to enhance matching performances of delay cells and thus reach high conversion linearity regardless of the process technology, which is a strong aspect of the approach. Simulations results show that the TDC achieves a timing resolution of 12 ps rms in a long 12.5 ns timing window, a low core power consumption of 4.8 mW and estimated differential and integral nonlinearities (DNL and INL) of 0.73 and 2.02 LSB with a standard deviation of 0.17 and 0.94 LSB respectively. The TDC, implemented in 0.13 mm CMOS technology, occupies a total silicon area of 1.83 $$\times $$× 2.23 mm$$^2$$2 including pads. Such a TDC will find useful applications in tomographic systems, where several time-correlated single photon counting (TCSPC) channels need to be used in a massively parallel configuration such as in diffuse optical tomography or in time-of-flight positron emission tomography.

A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20 × 2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/−1 LSB, 1/−1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases.

A 10-bit 1.8 V 45 mW 100 MHz CMOS transmitter chip for use in an XDSL modem in a home network

This paper describes a 10-bit 1.8 V 45 mW 100 MHz transmitter chip (TX chip) that is fabricated using 0.18 μm 1P6 M CMOS technology for use in an xDSL modem in a home network. The chip is composed of a 10-bit segmented digital-to-analog converter (DAC) and a fully differential adaptive line driver (LD). In designing the DAC, the switched-current method is used to increase the conversion speed; the anti-process-variation current cell with threshold-voltage compensation is used to reduce the linearity error, and the current cell, with differential input and gain boosting, is used to minimize the feedthrough error and tapered error distribution. The circuit layout of the current source has four-phase symmetry, not only to increase the linearity but also to eliminate the gradient error. To design a fully differential adaptive LD, the feed-forward capacitor and quiescent current control circuit are used to reduce the zero-crossing distortion and to minimize the second-order harmonic. Additionally, the power efficiency is increased using an output-impedance matching circuit. Measurements reveal that, for a TX chip at a differential load of 100 Ω and a supplied voltage of 1.8 V, the efficient number of bits, operating frequency, output voltage, output current, power consumption, differential nonlinearity error and integral nonlinearity error are 9 bits, 100 MHz, ± 0.874 V, ± 10 mA, 45.8 mW, ?0.80 to +0.62 LSB, and ?0.92 to +0.82 LSB, respectively.

A capacitance‐ratio quantification design for linearity test in differential top‐plate sampling sar ADCS

SummarySuccessive approximation register (SAR) analog‐to‐digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance‐ratio quantification design for the linearity test of differential top‐plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from −0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from −0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance‐ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd.

A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply.

A 10-bit 110 kS/s 1.16 &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$\mu\hbox{W}$&lt;/tex-math&gt; &lt;/inline-formula&gt; SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications

A 10-bit 110-kS/s successive-approximation analog-to-digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, a low-complexity calibration technique, a hybrid single/differential digital-to-analog converter architecture, and an attenuation capacitor with low sensitivity to mismatch errors. Fabricated in 180-nm CMOS, this ADC consumes a total power of 1.16 μW from 1.5 V/1.2 V analog/digital power supplies. The integral nonlinearity is between -1.23 LSB and 1.19 LSB, whereas the differential nonlinearity is between -0.71 LSB and 0.92 LSB. The ADC signal-to-noise-and-distortion ratio and spurious-free dynamic range are 56.1 and 67 dB with a 39.5-kHz sinusoid input, respectively. The ADC figure-of-merit is of 20 fJ per conversion step, which is very competitive, as compared with state-of-the-art ADCs in similar 180-nm CMOS technologies.

The Soft-Injection-Locked Ring Oscillator and Its Application in a Vernier-Based TDC

A time-to-digital converter (TDC) plays an important role in time interval measurement. Among various TDC structures, the Vernier-based TDC (VTDC) is promising because the time resolution of it depends on the frequency difference between the oscillators, not on the absolute oscillating frequency values. However, the oscillators used in the conventional VTDC require complicated calibration procedures. This makes the TDC system complex. This paper employs a new soft-injection-locked ring oscillator as the clock source for the VTDC. The proposed oscillator can oscillate immediately and accurately right after the triggering signal arrives. The TDC structure employing the purposed oscillators is verified by the TSMC 0.18μm CMOS process. The measured differential nonlinearity is within ±0.4 LSB and the measured integral nonlinearity is within ±0.8 LSB. The power consumption is 27.8 mW. The chip's core area is around 0.095 mm 2 . When the supply voltage varies from 1.75 to 1.85 V, the resolution deviation is less than ±0.18 LSB.

A 10-bit current-steering CMOS digital to analog converter

This paper proposed a 10-bit digital-to-analog converter consisting of a segmented current-steering architecture, with five different sizes of current source.The proposed 10-bit digital-to-analog converter was implemented using TSMC CMOS 0.35μm 2P4M technology. The power consumption was approximately 7.9mW at the sample rate of 200MHz, and the supply voltage was 3.3V. It achieved a DNL (differential nonlinearity) and an INL (integral nonlinearity) of 0.16 LSB and 0.13 LSB, respectively. The measured SFDR (spurious free dynamic range) was 45.3dB under a 1MHz sine waveform.This work presented a good performance compared with other researches in DNL, INL and power consumption.

A 10 bit, 300 MS/s Nyquist Current-Steering Power DAC With 6 V&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$_{\rm PP}$&lt;/tex&gt; &lt;/formula&gt; Output Swing

A 10 bit current-steering, digital-to-analog converter (DAC) is presented that delivers 6 V $_{\rm PP}$ into a 100 Ω differential load. To realize high-voltage swings using fineline CMOS, a stacked-FET buffer is used to isolate the current source from the output load. The stacked-FET buffer degrades the linearity of the DAC. This work presents a Volterra analysis to capture the frequency-dependent behavior of the stacked-FET circuit that can be cascaded to quantify the linearity of an $N$ -device stack. The power DAC is implemented in 45 nm CMOS SOI and the measured differential nonlinearity (DNL) and integral nonlinearity (INL) is better than 0.4 and 0.6 LSB, respectively. The DAC consumes 476 mW and achieves a peak SFDR of 73 dB and a minimum IM3 of $-$ 69 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a high-resolution ( $>$ 8 bit), high-speed ( $>$ 100 MS/s) DAC.

A method to correct differential nonlinearities in subranging analog-to-digital converters used for digital γ-ray spectroscopy

The influence on γ-ray spectra of differential nonlinearities (DNL) in subranging, pipelined analog-to-digital converts (ADCs) used for digital γ-ray spectroscopy was investigated. The influence of the DNL error on the γ-ray spectra, depending on the input count-rate and the dynamic range has been investigated systematically. It turned out that the DNL becomes more significant in γ-ray spectra with larger dynamic range of the spectroscopy system. An event-by-event offline correction algorithm was developed and tested extensively. This correction algorithm works especially well for high dynamic ranges.

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01pVs. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33LSB and a differential nonlinearity (DNL) of 0.14LSB. The DAC can achieve a maximum measured SFDR of 65.19dB for 97.50kHz signal at a sampling rate of 100MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07MHz signal the measured SFDR is 56.84dB at 100MSPS sampling rate. At 50MSPS sampling frequency and 146kHz signal the SFDR of the DAC is 65.90dB. The measured SFDR at 538kHz signal is 63.62dB for a sampling rate of 50MSPS. Measured third order intermodulation distortion of the DAC is 58.55dB, for a dual tone test with 1.03MHz and 1.51MHz signals at 50MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06MHz signal and 100MSPS sampling frequency, the power dissipation of the DAC is 20.74mW with 1.8V supply.

An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors

This work proposes a 12 b 10 MS/s 0.11 μm CMOS successive-approximation register ADC based on a C-R hybrid DAC for low-power sensor applications. The proposed C-R DAC employs a 2-step split-capacitor array of upper seven bits and lower five bits to optimize power consumption and chip area at the target speed and resolution. A VCM-based switching method for the most significant bit and reference voltage segments from an insensitive R-string for the last two least significant bits minimize the number of unit capacitors required in the C-R hybrid DAC. The comparator accuracy is improved by an open-loop offset cancellation technique in the first-stage pre-amp. The prototype ADC in a 0.11 μm CMOS process demonstrates the measured differential nonlinearity and integral nonlinearity within 1.18 LSB and 1.42 LSB, respectively. The ADC shows a maximum signal-to-noise-and-distortion ratio of 63.9 dB and a maximum spurious-free dynamic range of 77.6 dB at 10 MS/s. The ADC with an active die area of 0.34 mm2 consumes 1.1 mW at 1.0 V and 10 MS/s, corresponding to a figure-of-merit of 87 fJ/conversion-step.

Integrated Multichannel Electronics for High Performance Time Correlated Single Photon Counting

The analysis of extremely weak, ultrafast and periodical light signals is increasingly widespread in a large number of fields, from chemistry and biology to telemetry and communication, and in a great variety of applications, from quantum cryptography to fluorescence imaging.Speaking of fluorescent lifetime analysis, for example, the detection of very faint and fast optical signals is fundamental to investigate the complex interactions between molecules that play a key role in many crucial issues such as the origin and growth mechanisms of tumors. In this domain the Time-Correlated Single Photon Counting (TCSPC) technique is very effective to reconstruct the light waveform when both extremely high time resolution and linearity are required.TCSPC is based on the detection of single photons and on the record of their arrival times: if the probability of detecting a photon during one excitation cycle is far less than one, the histogram of photon arrivals per time bin exactly corresponds to the temporal trend of the light signal. In order to properly reconstruct the light waveform a time measurement block featuring very high performance is necessary: this circuit has to be able to measure time intervals of few hundreds of nanoseconds with picosecond time resolution and a differential non-linearity much lower than few percents of the time bin width.Moreover a growing number of techniques do now require to collect data from multiple channels at the same time. Förster Resonance Energy Transfer (FRET), Fluorescence Diffuse Optical Tomography (FDOT) and single-molecule spectroscopy, for example, can benefit a lot of a system capable of providing simultaneous analysis in temporal or spectral range. Indeed, concurrency not only reduces the measurement time, revealing dynamic phenomena even on very short timescales but it also opens the way to spectrally resolved measurements that analyze different events occurring simultaneously, like Fluorescence Cross-Correlation Spectroscopy (FCCS).Nevertheless the development of a truly parallel acquisition system featuring both high performance and a high number of independent channels is still an open challenge: to achieve this goal the design of a time measurement circuit capable of acquiring data from several channels in parallel while providing high performance on each channel is of the utmost importance. In this work a fully integrated array of 16 time to amplitude converters (TAC) designed in 0.35µm SiGe technology is presented.The first simulations show very high performance on each channel with a FWHM time resolution lower than 19ps and a differential non linearity lower than 0.4% peak-to-peak of the LSB. In order to reduce the overall area of the chip, pairs of converter stages share all the conversion chain through a 2 input multiplexer. The simulated dead time on the entire full scale range is 191ns, corresponding to a maximum conversion frequency of 5.24MHz per channel. The obtained results on the designed 16 channel TAC array are extremely good and, if the performance are verified by experimental measurements, this array will be one of the fundamental blocks of a fully parallel high-performance TCSPC acquisition system. Based on high efficiency fully custom single photon detectors (SPAD) and on a front-end electronics specifically designed to properly work with these sensors, the final system will be the upgrade of a few channels high performance acquisition chain already developed in the same technology.

A field-programmable-gate-array based time digitizer for the time-of-flight mass spectrometry.

The time-of-flight (TOF) mass spectrometry is one of the most widely used techniques to get information about the composition and structure of compounds. The time digitizer, based on time-to-digital conversion, is one of the important parts in modern TOF mass spectrometry, which is often implemented with analog circuitry or application-specific-integrated-circuit (ASIC) devices. However, it is difficult to achieve a high density with the analog approach. Furthermore, ASIC requires a long design cycle and the function cannot be easily revised for different applications. In this work, we present a highly flexible, accurate, yet low-costing design of time digitizer which is based on a field-programmable-gate-array (FPGA) and time interpolation method. Test results indicate that the bin size of this time digitizer is 390 ps with an average standard deviation (about 150 ps). The differential nonlinearity is in the range of -0.10 to +0.05 LSB (least significant bit), and the measurement time range is larger than 107 s. Compared with other techniques, it reduces the system complexity while providing a good flexibility. In addition, this technique can also accommodate one or more STOP pulse measurements for each START pulse reference, enabling measurement of multiple times-of-flight with a common start trigger. Besides, a time stamp is recorded for each input pulse, rendering this time digitizer versatile in other applications. Moreover, because of the programmable characteristic of a FPGA, more functions can be integrated in the time digitizer, such as a trigger function, data transfer interface; the parameters such as the number of the channels. The measurement range can also be modified according to different requirements.

High-Performance Single Photon Avalanche Diode Array and Integrated Electronics for Time Correlated Single Photon Counting

Time Correlated Single Photon Counting (TCSPC) is a very effective measurement technique to perform the analysis of extremely weak and fast, periodical light signals. Based on the detection of single photons and on the measure of their arrival time within the period of the signal, TCSPC technique is increasingly widespread in a large number of fields, from medicine to chemistry and biology, and in a large number of applications such as single molecule fluorescence spectroscopy, fluorescence imaging, and laser scanning microscopy.Nowadays, most of the high-performance TCSPC systems are focused on single channel applications and the use of multiple parallel acquisition chains is necessary to obtain a multidimensional system, , with very high costs and large occupied areas. It is therefore necessary to develop new acquisition systems based, on the one hand, on detectors with high quantum efficiency and suitable for parallel operation, and, on the other hand, on electronics intrinsically designed to simultaneously acquire data from multiple channels. Concerning the first aspect, Single Photon Avalanche Diodes (SPADs) proved to be a valid alternative to PMTs in many applications, from quantum cryptography to astrophysics and biology.Recent systems for single-photon timing applications typically present a trade-off between number of channels and performance: the higher the number of channels, the poorer the obtained performance on each channel.In order to overcome this trade-off, in this work we present the development of the detector and the electronics necessary to develop photon timing systems featuring a large number of channels in conjunction with high performance. Starting from the SPAD developed in our lab in the last years, it is important to develop all the integrated electronics to extract and elaborate the timing information. First of all, a circuit capable of reading directly the avalanche current coming from the detectors is of the utmost importance in order to achieve a very high temporal resolution while minimizing the crosstalk between adjacent channels. Thus, a fully integrated trans-impedance stage has been designed in 180nm Si-Ge with a gigahertz bandwidth in order to obtain few tens of picoseconds full width at half maximum resolution and negligible crosstalk between different channels. Secondly, a fully integrated array of high performance time-to-amplitude converters (TAC) has been designed. In fact, in any TCSPC application one of the most important section in the acquisition chain is the time measurement block. Three main performances are required in the time measure to reconstruct the analyzed signal without introducing distortions: a high temporal resolution (in the order of few tens of picoseconds), a differential nonlinearity (DNL) of few percent of the histogram channel width and a high measurement rate (in the Megahertz order).Finally, in order to develop a fully parallel and compact TCSPC system, resource sharing is mandatory. To achieve thisgoal an integrated chip capable of routing the signal coming from the trans-impedance stage towards the timemeasurement circuit has been designed in 180nm Si-Ge technology. Since the probability of detecting a photon during one excitation cycle in any TCSPC measurement is far less than one, we have designed the routing logic to connect theSPAD to one of the TAC converters only if a photon has been detected, thus allowing the system to have a number ofTAC converters lower than the detectors one.The design of these three main blocks in conjunction with fully custom high efficiency SPAD arrays opens the way to the development of a TCSPC acquisition system that can feature both a very high number of parallel channels and very high performance.

A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.