An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

Abstract

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01pVs. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33LSB and a differential nonlinearity (DNL) of 0.14LSB. The DAC can achieve a maximum measured SFDR of 65.19dB for 97.50kHz signal at a sampling rate of 100MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07MHz signal the measured SFDR is 56.84dB at 100MSPS sampling rate. At 50MSPS sampling frequency and 146kHz signal the SFDR of the DAC is 65.90dB. The measured SFDR at 538kHz signal is 63.62dB for a sampling rate of 50MSPS. Measured third order intermodulation distortion of the DAC is 58.55dB, for a dual tone test with 1.03MHz and 1.51MHz signals at 50MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06MHz signal and 100MSPS sampling frequency, the power dissipation of the DAC is 20.74mW with 1.8V supply.