Differential Linearity Error Research Articles

Laser Shearing-Interferometry for Measurement of Rail Straightness Accuracy and Error Analysis

A long rail straightness measurement method is given for the portable laser alignment measurement system which is based on laser shearing interference fringes. Through theoretical derivation, mathematical model is set up between the laser phase differential linearity error and shearing interferometry. Large numbers of experiments have verified correctness of long rail straightness measurement method, analyzed the cause of error and provided ways for error reduction.

Micromechanical Digital-to-Analog Converter for Out-of-Plane Motion

This paper describes a novel micromechanical digital-to-analog converter (MDAC) for out-of-plane motion using electrostatic parallel-plate actuators. The proposed mechanism converts an N-bit digital signal to a mechanical out-of-plane displacement that is proportional to the analog value represented by the N-bit binary word. The mechanism is analogous to that of an electrical binary-weighted-input digital-to-analog converter (DAC). It consists of a movable platform, an array of parallel-plate microactuators each operating in an ON/OFF mode and a set of connection springs that connect the actuators to the platform. The spring constants of the connection springs are weighted so that the stiffness of successive springs is related by a factor of 2. A 4-bit mechanism has been fabricated using the Poly-MUMPS process, achieving a total stroke of 675 nm (full-scale output) and step size (LSB) of 45 nm in a highly repeatable and stable manner. The linearity error (LE) of the device is within /spl plusmn/0.28 LSB, and the differential linearity error (DLE) is within /spl plusmn/0.25 LSB. This mechanism can be configured for many promising applications, particularly in optical devices and systems such as tunable external cavity diode laser, tunable VCSELs, adaptive micromirror array and tunable wavelength filter.

Optimal selection of test vectors for DA converter testing

A method of digital noise coupling reduction is discussed to highlight the fact that analog circuits may not work properly unless measures are taken to minimize the digital noise that is coupled to the analog circuit portions of a mixed analog–digital silicon die. Mixed analog–digital simulation is also discussed to ensure that correct functionality and specifications are obtained. Accessibility to the embedded digital-to-analog converter (DAC) digital input nodes is obtained by means of wrapper cells or direct access via package pins and accessibility to the analog output of the DAC is obtained by bringing the analog output to a package pin. Details of the testing methodology for an 8-bit DAC are presented. This methodology tests for correct functionality, 100% fault coverage with respect to all of the current sources in the DAC, simultaneously switching noise-induced errors and differential linearity errors. Consideration is also given to make sure that the test time in a mass production environment is minimized for cost reason.

A 10-bit 80 MHz 3.0 V CMOS D/A converter for video applications

A low-voltage, high-speed, and high-resolution CMOS D/A converter is implemented using an improved unique switching sequence to reduce integral linearity error (ILE) in the output of current cells, and a novel segmented layout technique to minimize both current asymmetry due to drain current directions and voltage drop due to power line resistance. The D/A converter has been fabricated by using 0.65 /spl mu/m CMOS process. The differential linearity error (DLE) is 0.37 LSB and the ILE is 0.87 LSB. It occupies a die area of 700/spl times/800 /spl mu/m/sup 2/ and operates up to 80 MHz with 3.O V.

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 /spl mu/m single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV/spl middot/s and the settling time within /spl plusmn/0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm/spl times/1.2 mm (1.75 mm/spl times/0.7 mm for the DAC portion). >

A 10-bit 70 MHz 3.3 V CMOS 0.5 μm D/A converter for video applications

A 10-bit D/A converter with differential current outputs is presented. Special care was taken to minimize the output glitch energy and the linearity errors, considering the 1.5 V output range under a 3.3 V voltage supply. A current cell with biased switches, thermometer decoding and a shuffle in the physical layout of the cells enabled to achieve the following performances. The integral and differential linearity errors INL and DNL are within +/-1.5 LSB and +/-0.5 LSB respectively. The maximal glitch energy is 60 pV.S. The device dissipates 46 mW at 70 MHz clock rate and full-scale output swing. The D/A converter has been developed in a CMOS 0.5 /spl mu/m technology. The active chip area is 0.4 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources

This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-/spl mu/m double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to /spl plusmn/1/2 LSB is within 8 ns. The chip area is 1.8 mm/spl times/1.0 mm. >

A 130-MHz 8-b CMOS video DAC for HDTV applications

In order to achieve monotonicity and a high-speed performance, a current-cell matrix configuration and a parallel decoding circuit with one-stage latches have been used. A deglitching circuit has been introduced in the decoding stages to guarantee a low glitch energy. P-channel devices used as current sources ensure a low noise level and a ground-referenced voltage output in a doubly terminated 75- Omega transmission line. Experimental results have shown that the maximum conversion rate is 130 MHz and the integral and differential linearity errors are less than 0.5 LSB. The maximum glitch energy is 50 pS-V. The DAC has been developed in a 1- mu m digital/analog CMOS technology. The entire circuit dissipates 150 mW at a 130-MHz conversion rate while operating from a single 5-V power supply.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 10-b 70-MS/s CMOS D/A converter

A 10-b 70-MS/s CMOS D/A converter fabricated in a 1- mu m CMOS technology is described. An integral linearity error caused by error distributions of current sources is reduced by a new switching sequence called hierarchical symmetrical switching. A differential linearity error caused by an off-axis drain-source implantation is reduced by the layout technique of current sources. The D/A converter is fabricated by using a single-polycide double-metal standard digital process. Both the integral and the differential linearity errors are less than +or-0.5 LSB. The settling time to +or-0.1 % is less than 14 ns. The worst-case glitch energy is approximately 60 pV-s. This D/A converter has a single power supply of 5 V and dissipates 170 mW at 70 MS/s. The chip size is 2.02 mm*1.87 mm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A four-channel ADC on a VME board

A four-channel analog-to-digital converter (ADC) for data acquisition in nuclear physics experiments has been developed on a VME board. The circuit architecture is a multistretcher configuration based on a fast conversion module. The board can operate either in sampling or in autotrigger mode with an input range of 4.096 or 8.192 V; the risetime protection can vary from 1 to 32 mu s. Many functions are software selectable; the most significant are: the linear gate trigger mode, the risetime protection, and the ability to set of the low and high thresholds independently for each channel. The conversion module is based on a two-step concept: an overall resolution of 12 b, with a conversion time lower than 1 mu s, is obtained by means of two 8-b flash ADCs and a sliding-scale compensation technique is used to improve the differential linearity. The differential linearity error is less than 1%, while the integral linearity error is 0.023% over the 98% of the dynamic range. >

A four-channel ADC on a VME board

A four-channel analog-to-digital converter (ADC) for data acquisition in nuclear physics experiments has been developed on a VME board. The circuit architecture is a multistretcher configuration based on a fast conversion module. The board can operate either in sampling or in autotrigger mode with an input range of 4.096 or 8.192 V; the risetime protection can vary from 1 to 32 mu s. Many functions are software selectable; the most significant are: the linear gate trigger mode, the risetime protection, and the ability to set of the low and high thresholds independently for each channel. The conversion module is based on a two-step concept: an overall resolution of 12 b, with a conversion time lower than 1 mu s, is obtained by means of two 8-b flash ADCs and a sliding-scale compensation technique is used to improve the differential linearity. The differential linearity error is less than 1%, while the integral linearity error is 0.023% over the 98% of the dynamic range.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An 80-MHz 8-bit CMOS D/A converter

A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.

The calibration of a DAC using differential linearity measurements

The differential linearity adjustment procedure offers an accurate method of digital-to-analog converter (DAC) adjustment with only modest accuracy in the instrumentation. The author shows that the worst case error in linearity due to a differential linearity error (DLE) of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> in the upper <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> bits is bounded by <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ne</i> /3. Self-heating effects and output drive asymmetry can cause superposition errors which also degrade the linearity of the DAC. The effect of the resolution of the instrumentation on the final gain adjustment is shown to increase exponentially with the number of bits corrected.

Ternary-to-analog converters using resistor ladders

A description of ternary-to-analog (T/A) converters with high accuracy is given. These converters consist of the modified resistor ladder and some other circuit elements. The 5-trit T/A converter is constructed, and the results show that the maximum differential linearity error is 0.1 least significant trit (LST).

Testing digital/analog and analog/digital converters

This paper describes several D/A and A/D converter test circuits which range from simple and low-cost to fully automatic and expensive. Methods are presented to measure the more important specifications of offset, gain, full scale, linearity, and differential linearity errors. The discussions focus on, but are not limited to, testing 12-bit converters. Guidelines are given for determining the required accuracy of the measurement standard and for using proper circuit layout and wiring. Part of the test circuits are static and use a DVM as a reference. Other testers are dynamic and use a fast-settling D/A converter as a reference. Many of the circuits are manually operated, but others are automated using a computing controller. The unique characteristics of converters such as the symmetrical error patterns and the dynamic errors are discussed in light of how they relate to the techniques chosen to measure the errors. Part of the test methods assume that the weight of each bit in a converter is completely independent of the on/off state of the other bits (low superposition errors). When superposition errors are not small, they must be considered before choosing a test method. In general, the intent of this paper is to lay enough ground work so that the user of converter products can implement a test system that is both economical and sufficient to produce the desired results.

Very Precise 30 Nanosecond Linear Gate

After a short theoretical exposition of a method for compensating inaccuracies in parallel-diode switch-gates, a linear gate circuit is presented which is based on the described principle. Accurate measurements of differential linearity error in the whole dynamic range (0–10 V) have been done. The results of experimental checks of rise time, pedestal, rejection factor, and thermal stability are also given. The circuit which operates with gating pulses longer than 30 nsec is believed to introduce a considerable improvement in comparison with previously given solutions, mainly from the linearity point of view.