In modern days, integrated circuits are facing different challenges with its high speed features. One of the big challenges is EMI emission from electronic devices. Different regulatory bodies like US (FCC), EN etc have strict regulations aim at limiting the amount of EMI radiations. On the designer’s point of view, these effects can range from a simple degradation of a specific signal to a total loss of data. To increase chip performance the clock speed is needed to be increased which gives rise to EMI immensely, however different approaches in the design cycle can successfully limit the emission at an expected level. This paper analyses different approaches for significant low cost reduction mechanisms. For higher data rates like 8 GT/s or 16 GT/sClock scrambling, Clock dithering, spread spectrum clocking, differential clocking and using clock buffers etc are the most beneficial methods especially for the faster System on Chip (SoC). KeywordsEMI, Clock scrambling, spread spectrum, EMI emissions, EMI reduction, Dithering Ckt etc.