A 40-Gb/s Full-Rate 2:1 MUX in 0.18-$\mu{\hbox {m}}$ CMOS

Abstract

This paper demonstrates high-speed design techniques that enable realization of a full-rate broadband serializer operating at 40 Gb/s using a 0.18-μm CMOS process. Bandwidth enhancement techniques, including shunt-peaking and multipole bandwidth enhancement, have been incorporated in the different high-speed blocks in the serializer. A dynamic retiming circuit capable of clocked 40-GHz operation is presented, which reduces the periodic jitter at the serial output. A low-power distributed buffer with unequal characteristic impedances in the gate line and drain line is designed as a 40-Gb/s output buffer. A method for generating a differential 40-GHz clock using two coupled 20-GHz oscillators with a “push-push” topology is also presented. An injection-locked divider based on a four-stage ring oscillator with four injection points has been designed for generating a 10-GHz clock signal.