Differential Cascode Voltage Switch Research Articles

Design of energy‐efficient ternary circuits using differential cascode voltage switch strategies in carbon nanotube field effect transistor technology

Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS-based ternary logic gates and unary operators are reported using static diode voltage divider topology. The main focus of the proposed ternary designs using DCVS logic style is to provide minimum energy consumption with less area overhead. In the presented method, a new power efficient and compact solution is being provided to improve the driving capability of the ternary DCVS circuits. All the simulations are performed on HSPICE synopsis simulator using 32 nm technology under different operational conditions. For the inversion and logical operations, the proposed method has a maximum power reduction of 45% and an energy reduction of 30% as compared to earlier reported DCVS designs. In the case of shifting operators, the maximum power reduction of 38.93% and an energy reduction of 39% are achieved. The design performance is robust when subjected to various process variation effects and have sufficient noise margins.

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications.

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

SummaryTranslating the analog input voltage to delay of delay cells is a necessity for realizing digital time‐based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross‐coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross‐coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see‐saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short‐circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all‐digital time‐based analog to digital converter (ADC). The proposed 4‐bit ADC, implemented in TSMC 65‐nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm2.

Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques

A shallow-depth differential source coupled logic is proposed in this paper, targeting low-voltage high-speed applications. In this logic, the number of transistor stages decreases from supply voltage to ground. This feature offers performance advantage over DCVSL (Differential Cascode Voltage Switch Logic) and DSCL (Differential Static CMOS Logic) styles in a circuit block. Using 180 and 65-nm standard CMOS technologies, the proposed logic demonstrates an average speed-up of 30% over CVSL (Cascode Voltage Switch Logic) based structures in the low-voltage region due to fewer series stages between supply voltage and ground nodes with near EDP (Energy-Delay Product) to its DSCL counterpart. Simulation and post-layout simulation results of 8-bit carry chain generator show that the proposed logic is 31, 23 and 13% faster than the DCVSL, DSCL and MTCML (Multiple-Tailed CML) carry generator chain, respectively. Proposed logic also demonstrates 7% and 6% PDP (power-delay product) reduction than DCVSL and DSCL carry generator chain, respectively.

Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

MOS switch-based DPA-resistant GF(28) modulo multiplier

ABSTRACTConventional design of cryptographic integrated circuits is vulnerable to differential power analysis (DPA). Mostly XOR gates are used for performing cryptographic computations. By observing the side channel information adversary can retrieve secret information. Data processing power of conventional gates are directly proportional to input bits transition, which are used by DPA attacker. To overcome this problem, this paper proposes DPA resistant modulo multiplier using MOS-switches and double switch differential cascode voltage switch logic (DS-DDCVSL). Proposed implementation gives minimum bit transition in those gates. It scrambles computational power irrespective of input bit patterns and shows constant power trace and makes the implementation DPA resistant.

On Improving the Performance of Dynamic DCVSL Circuits

This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.

Low energy/delay overhead level shifter for wide‐range voltage conversion

SummaryMulti‐supply voltage systems on chip have been widely explored for energy‐efficient elaborations. A main challenge of multi‐supply voltage designs is the interfacing of digital signals coming from ultra‐low‐voltage core logics to higher power supply domains and/or to input/output circuits. In this work, we propose an energy/delay‐efficient level shifter architecture that is capable of converting extremely low levels of input voltages to the nominal voltage domain. In order to limit static power, the proposed circuit is based on the single‐stage differential cascode voltage switch scheme. To improve switching speed and dynamic energy consumption, our design dynamically adapts the current sourced by the pull‐up network on the basis of the occurring transition. A test chip was fabricated in 180 nm complementary metal–oxide–semiconductor technology to verify the proposed technique. Measurement results show that our design is capable of converting 100 mV of input voltages to 1.8 V, while assuring an average propagation delay of about 26 ns, an average static power of 100 pW, and an energy per transition of 140 fJ for the target voltage‐level conversion from 0.4 to 1.8 V. Copyright © 2016 John Wiley & Sons, Ltd.

FAST LOW POWER FREQUENCY SYNTHESIS APPLICATIONS BY USING A DCVSL DELAY CELL

In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) pull-up stage. In conventional DCVSL structure these lies a drawback i.e. low-to-high propagation delay is larger than high-to-low propagation delay which could be reduced by using DCVSL-R. Using resistors in DCVSL-R structure, parasitic effects are coming into picture and it occupies more area on the chip [1]. To minimize these problems we propose a new Ultra Low Power Diode (ULPD) structures in place of resistors. This provides the minimum parasitic effects and occupies less area on the chip. Second one uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This is an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using cadence and model parameters of a 180nm CMOS process. This simulation result of the two circuits is presented and is compared. These circuits are suitable for VLSI implementation. Secondly, we proposed two new CMOS Schmitt trigger circuits. These Schmitt trigger circuits are evaluated both analytically and numerically with the sources from proposed ULPD ring oscillators. The hysteresis curves of the circuits are presented. The Schmitt triggers introduced here are most suitable for high speed applications. The proposed circuits havebeen designed in TSMC-0.18μm 1.8v CMOS technology and analyzed using spectre from cadence Design systems at 50MHz and 103MHz.

A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI attribute. Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. Thirdly, we propose a microcell-interleaving genetic algorithm (MIGA) to stochastically optimize the proposed microcell-interleaving approach on power dissipation, transistor count, and delay. To validate the proposed design approach, a complete performance profile of ISCAS-85 C499 circuit is investigated on the basis of differential cascode voltage switch logic (DCVSL) and dynamic strong indicating (DSI) microcells. We demonstrate the efficiency of the proposed design approach by benchmarking against the competing DCVSL, null convention logic and DSI designs on five ISCAS-85 circuits. Specifically, the proposed designs, on average, are 1.77 × better in power dissipation, 1.4 × better in area, and 1.58 × better in a composite metric of power × area × delay, and reasonably slower for the lowest power dissipation points. We further demonstrate the practicality of the proposed design approach by implementing an 8-tap 16-bit asynchronous QDI finite impulse response filter. Finally, we demonstrate the ~10% and ~11% improved efficiency of the proposed MIGA over the greedy algorithm and dynamic programming, respectively.

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic

Differential Cascode Voltage Switch (DCVS) is a well-known logic style, which constructs robust and reliable circuits. Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics. While one of the strategies leads to fewer transistors, the other one has higher noise margin. New designs are simulated with HSPICE and 32nm CNTFET technology at various realistic conditions such as different power supplies, load capacitors, frequencies, and temperatures. Simulations results demonstrate their robustness and efficiency even in the presence of PVT variations. In addition, new noise injection circuits for ternary logic are also presented to perform noise immunity analysis.

ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

Ultra Low Power Asynchronous Charge Sharing Logic

Asynchronous logic enables significant power reduction and high robustness in digital design. In this paper, a novel Asynchronous Charge Sharing Logic (ACSL) is proposed to achieve ultra-low dynamic and static power with little trade-off in performance. ACSL combines adiabatic logic with charge sharing technology so that the penalty of power clock generator in adiabatic circuit is eliminated while nearly 50% energy transferring efficiency is obtained. Also, by discharging all internal nodes to ground in idle mode, a saving of 75% of static power of a one-bit full adder is achieved while compared to the popular Domino Differential Cascode Voltage Switch Logic (DDCVSL) adder. Some 8-bit multipliers are built based on ACSL, PFAL (Positive Feedback Adiabatic Logic), DDCVSL and dual-rail Domino logic. All our implementations results are reported for the 45 nm CMOS process. At least 30% dynamic power reduction and more than 24% improvement of the Power-Delay Product are achieved compared to other three types of logic. Significant leakage power reductions of more than 30% can be also achieved.

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder

A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder

Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter

In this paper, high-voltage (HV)-tolerant level shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to constrain the output using a logic function during out of the normal mode periods (power-up, power-down, reset, etc.). These HV-tolerant logic circuits were used in the power block of a buck converter designed in a standard 3.3-V 0.13-mum CMOS process, powered by an input voltage range from 2.7 to 4.2 V. Simulation and experimental results of the buck are analyzed, and the topology is evaluated.

Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS

This paper presents a 4-b low-power, low-voltage flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H); 2)differential comparator; and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current-mode dual-array structure to reduce the aperture jitter for high-input signal frequency. The differential comparator eliminates the use of the resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits, which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared with the conventional ROM encoder. The ADC is designed in 130-nm CMOS technology. Fast Fourier transform tests prove proper operation of the ADC sampled at 2.5 GHz for the input signal frequency up to 1 GHz

An asynchronous 32×8-bit multiplier based on LDCVSPG logic

An asynchronous high-speed pipelined 32×8-bit array multiplier based on latched differential cascode voltage switch with pass-gate (LDCVSPG) logic is presented. The multiplier is based on 4-phase dual-rail protocol. HSPICE analysis using device parameters of Central Semiconductor Manufacturing Corporation (CSMC’s) 0.6 μm CMOS technology is also given, and the result shows that the average data throughput of the multiplier is 375 MHz.

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the leakage problems in PD/SOI DCVSL. The proposed low-swing DCVSL (LS-DCVSL) uses the small internal swing to prevent the body of evaluation transistors from being charged to high voltage and, hence, suppress the leakages in DCVSL. Simulation results show that the proposed LS-DCVSL five-input XOR circuit is 33% faster than DCVSL five-input XOR circuit. In addition, the proposed circuit does not experience noise margin reduction due to pass-gate leakage.

Reducing radiation-hardened DigitalCircuit power consumption

Low-power radiation-hardened sequential digital circuits supporting multiple supply voltages, integrated logic, and a low standby power state are presented. By basing the design on proven radiation hard circuits, single event effects hardness is guaranteed. The circuit is based on differential cascode voltage switch logic, which provides an integral level shift and allows storage at the full supply voltage supported by the process, while allowing the combinatorial logic supply voltage to scale for power savings. When compared to a conventional master-slave flip-flop design, the proposed flip-flop design provides up to 80% energy reduction with logic operating at reduced voltage and speed. Fifty-percent energy reduction is obtained without compromising speed when operating with all circuits at maximum voltage.