Abstract
ABSTRACTConventional design of cryptographic integrated circuits is vulnerable to differential power analysis (DPA). Mostly XOR gates are used for performing cryptographic computations. By observing the side channel information adversary can retrieve secret information. Data processing power of conventional gates are directly proportional to input bits transition, which are used by DPA attacker. To overcome this problem, this paper proposes DPA resistant modulo multiplier using MOS-switches and double switch differential cascode voltage switch logic (DS-DDCVSL). Proposed implementation gives minimum bit transition in those gates. It scrambles computational power irrespective of input bit patterns and shows constant power trace and makes the implementation DPA resistant.
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