Differential Cascode Voltage Switch Logic Research Articles

Design of energy‐efficient ternary circuits using differential cascode voltage switch strategies in carbon nanotube field effect transistor technology

Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS-based ternary logic gates and unary operators are reported using static diode voltage divider topology. The main focus of the proposed ternary designs using DCVS logic style is to provide minimum energy consumption with less area overhead. In the presented method, a new power efficient and compact solution is being provided to improve the driving capability of the ternary DCVS circuits. All the simulations are performed on HSPICE synopsis simulator using 32 nm technology under different operational conditions. For the inversion and logical operations, the proposed method has a maximum power reduction of 45% and an energy reduction of 30% as compared to earlier reported DCVS designs. In the case of shifting operators, the maximum power reduction of 38.93% and an energy reduction of 39% are achieved. The design performance is robust when subjected to various process variation effects and have sufficient noise margins.

Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

An efficient voltage to delay conversion method for DCVSL cells and its application in high speed all‐digital time‐based quantization

SummaryTranslating the analog input voltage to delay of delay cells is a necessity for realizing digital time‐based quantization. Usually, this conversion is done through additional elements, imposing extra power and area. This paper proposes a voltage to delay conversion method for cross‐coupled differential cascode voltage switch logic (DCVSL) cells, without adding any extra elements to their basic structures. Cross‐coupled delay cells are superior to conventional CMOS inverters in terms of lower power consumption, propagation delay, and area. However, controlling their delay is a demanding task due to their asynchronous charging and discharging. The key features of the proposed method are (a) controlling the delay of DCVSL cells just by see‐saw changing of PMOS transistors source voltages; (b) reducing the propagation delays of DCVSL cells by simultaneously accelerating the charging and discharging processes; (c) reducing the power consumption by decreasing both the switching time and short‐circuit current; (d) employing the proposed voltage to delay conversion method to develop a low power, small area, all‐digital time‐based analog to digital converter (ADC). The proposed 4‐bit ADC, implemented in TSMC 65‐nm CMOS technology, consumes 0.37 mW at conversion speed of 2 GHz with SNDR 20.9 dB and SFDR 30.2 dB, and occupies an active area of 0.0029 mm2.

Design of low-voltage shallow-depth differential source coupled logic using feedback and feedforward techniques

A shallow-depth differential source coupled logic is proposed in this paper, targeting low-voltage high-speed applications. In this logic, the number of transistor stages decreases from supply voltage to ground. This feature offers performance advantage over DCVSL (Differential Cascode Voltage Switch Logic) and DSCL (Differential Static CMOS Logic) styles in a circuit block. Using 180 and 65-nm standard CMOS technologies, the proposed logic demonstrates an average speed-up of 30% over CVSL (Cascode Voltage Switch Logic) based structures in the low-voltage region due to fewer series stages between supply voltage and ground nodes with near EDP (Energy-Delay Product) to its DSCL counterpart. Simulation and post-layout simulation results of 8-bit carry chain generator show that the proposed logic is 31, 23 and 13% faster than the DCVSL, DSCL and MTCML (Multiple-Tailed CML) carry generator chain, respectively. Proposed logic also demonstrates 7% and 6% PDP (power-delay product) reduction than DCVSL and DSCL carry generator chain, respectively.

MOS switch-based DPA-resistant GF(28) modulo multiplier

ABSTRACTConventional design of cryptographic integrated circuits is vulnerable to differential power analysis (DPA). Mostly XOR gates are used for performing cryptographic computations. By observing the side channel information adversary can retrieve secret information. Data processing power of conventional gates are directly proportional to input bits transition, which are used by DPA attacker. To overcome this problem, this paper proposes DPA resistant modulo multiplier using MOS-switches and double switch differential cascode voltage switch logic (DS-DDCVSL). Proposed implementation gives minimum bit transition in those gates. It scrambles computational power irrespective of input bit patterns and shows constant power trace and makes the implementation DPA resistant.

On Improving the Performance of Dynamic DCVSL Circuits

This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.

FAST LOW POWER FREQUENCY SYNTHESIS APPLICATIONS BY USING A DCVSL DELAY CELL

In this paper, we proposed two new structures for differential cascode voltage switch logic (DCVSL) pull-up stage. In conventional DCVSL structure these lies a drawback i.e. low-to-high propagation delay is larger than high-to-low propagation delay which could be reduced by using DCVSL-R. Using resistors in DCVSL-R structure, parasitic effects are coming into picture and it occupies more area on the chip [1]. To minimize these problems we propose a new Ultra Low Power Diode (ULPD) structures in place of resistors. This provides the minimum parasitic effects and occupies less area on the chip. Second one uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This is an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using cadence and model parameters of a 180nm CMOS process. This simulation result of the two circuits is presented and is compared. These circuits are suitable for VLSI implementation. Secondly, we proposed two new CMOS Schmitt trigger circuits. These Schmitt trigger circuits are evaluated both analytically and numerically with the sources from proposed ULPD ring oscillators. The hysteresis curves of the circuits are presented. The Schmitt triggers introduced here are most suitable for high speed applications. The proposed circuits havebeen designed in TSMC-0.18μm 1.8v CMOS technology and analyzed using spectre from cadence Design systems at 50MHz and 103MHz.

A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)

In this paper, we propose a design approach to mitigate the hardware overhead of the data completion detection circuit in quasi-delay-insensitive (QDI) asynchronous-logic circuits. In this proposed design approach, three novelties are highlighted. Firstly, a novel microcell-interleaving approach is proposed to reduce the number of completion detection (CD) circuits while retaining the required QDI attribute. Secondly, we analyze the performance of the QDI circuits based on the proposed microcell-interleaving approach graphically in terms of power dissipation, transistor count and delay, and evaluate/determine the upper and lower boundaries of these performance profiles. Thirdly, we propose a microcell-interleaving genetic algorithm (MIGA) to stochastically optimize the proposed microcell-interleaving approach on power dissipation, transistor count, and delay. To validate the proposed design approach, a complete performance profile of ISCAS-85 C499 circuit is investigated on the basis of differential cascode voltage switch logic (DCVSL) and dynamic strong indicating (DSI) microcells. We demonstrate the efficiency of the proposed design approach by benchmarking against the competing DCVSL, null convention logic and DSI designs on five ISCAS-85 circuits. Specifically, the proposed designs, on average, are 1.77 × better in power dissipation, 1.4 × better in area, and 1.58 × better in a composite metric of power × area × delay, and reasonably slower for the lowest power dissipation points. We further demonstrate the practicality of the proposed design approach by implementing an 8-tap 16-bit asynchronous QDI finite impulse response filter. Finally, we demonstrate the ~10% and ~11% improved efficiency of the proposed MIGA over the greedy algorithm and dynamic programming, respectively.

ULPD and CPTL Pull-Up Stages for Differential Cascode Voltage Switch Logic

Two new structures for Differential Cascode Voltage Switch Logic (DCVSL) pull-up stage are proposed. In conventional DCVSL structure, low-to-high propagation delay is larger than high-to-low propagation delay this could be brought down by using DCVSL-R. Promoting resistors in DCVSL-R structure increase the parasitic effects and unavoidable delay and it also occupies more area on the chip (Turker et al., 2011). In order to minimize these problems, a new Ultra-Low-Power Diode (ULPD) structures in place of resistors have been suggested. This provides the minimum parasitic effects and reduces area on the chip. Second proposed circuit uses Complementary Pass Transistor Logic (CPTL) structure, which provides complementary outputs. This contributes an alternate circuit for conventional DCVSL structure. The performances of the proposed circuits are examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results of these two circuits are compared and presented. These circuits are found to be suitable for VLSI implementation.

Ultra Low Power Asynchronous Charge Sharing Logic

Asynchronous logic enables significant power reduction and high robustness in digital design. In this paper, a novel Asynchronous Charge Sharing Logic (ACSL) is proposed to achieve ultra-low dynamic and static power with little trade-off in performance. ACSL combines adiabatic logic with charge sharing technology so that the penalty of power clock generator in adiabatic circuit is eliminated while nearly 50% energy transferring efficiency is obtained. Also, by discharging all internal nodes to ground in idle mode, a saving of 75% of static power of a one-bit full adder is achieved while compared to the popular Domino Differential Cascode Voltage Switch Logic (DDCVSL) adder. Some 8-bit multipliers are built based on ACSL, PFAL (Positive Feedback Adiabatic Logic), DDCVSL and dual-rail Domino logic. All our implementations results are reported for the 45 nm CMOS process. At least 30% dynamic power reduction and more than 24% improvement of the Power-Delay Product are achieved compared to other three types of logic. Significant leakage power reductions of more than 30% can be also achieved.

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

In this paper, a low-cost, power efficient and fast Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cell (named DCVSL-R) is proposed. We use the DCVSL-R cell to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When compared to TSPC, DCVSL circuits offer small input and clock capacitance and a symmetric differential loading for previous RF stages. When compared to CML, they offer low transistor count, no headroom limitation, rail-to-rail swing and no static current consumption. However, DCVSL circuits suffer from a large low-to-high propagation delay, which limits their speed and results in asymmetrical output waveforms. The proposed DCVSL-R circuit embodies the benefits of DCVSL while reducing the total propagation delay, achieving faster operation. DCVSL-R also generates symmetrical output waveforms which are critical for differential circuits. Another contribution of this work is a closed-form delay model that predicts the speed of DCVSL circuits with 8% worst case accuracy. We implement two ring-oscillator-based VCOs in 0.13 μm technology with DCVSL and DCVSL-R delay cells. Measurements show that the proposed DCVSL-R based VCO consumes 30% less power than the DCVSL VCO for the same oscillation frequency (2.4 GHz) and same phase noise (-113 dBc/Hz at 10 MHz). DCVSL-R circuits are also used to implement the high frequency dual modulus prescaler (DMP) of a 2.4 GHz frequency synthesizer in 0.18 μm technology. The DMP consumes only 0.8 mW at 2.48 GHz, a 40% reduction in power when compared to other reported DMPs with similar division ratios and operating frequencies. The RF buffer that drives the DMP consumes only 0.27 mW, demonstrating the lowest combined DMP and buffer power consumption among similar synthesizers in literature.

Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter

In this paper, high-voltage (HV)-tolerant level shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to constrain the output using a logic function during out of the normal mode periods (power-up, power-down, reset, etc.). These HV-tolerant logic circuits were used in the power block of a buck converter designed in a standard 3.3-V 0.13-mum CMOS process, powered by an input voltage range from 2.7 to 4.2 V. Simulation and experimental results of the buck are analyzed, and the topology is evaluated.

A leakage-tolerant low-swing circuit style in partially depleted silicon-on-insulator CMOS technologies

The parasitic bipolar leakage and the large subthreshold leakage due to high floating-body voltage reduce the noise margin and increase the delay of the circuits in the partially depleted silicon-on-insulator (PD/SOI). Differential cascode voltage switch logic (DCVSL) has circuit topologies susceptible to the leakage currents. In this paper, we propose a new circuit style to effectively handle the leakage problems in PD/SOI DCVSL. The proposed low-swing DCVSL (LS-DCVSL) uses the small internal swing to prevent the body of evaluation transistors from being charged to high voltage and, hence, suppress the leakages in DCVSL. Simulation results show that the proposed LS-DCVSL five-input XOR circuit is 33% faster than DCVSL five-input XOR circuit. In addition, the proposed circuit does not experience noise margin reduction due to pass-gate leakage.

Reducing radiation-hardened DigitalCircuit power consumption

Low-power radiation-hardened sequential digital circuits supporting multiple supply voltages, integrated logic, and a low standby power state are presented. By basing the design on proven radiation hard circuits, single event effects hardness is guaranteed. The circuit is based on differential cascode voltage switch logic, which provides an integral level shift and allows storage at the full supply voltage supported by the process, while allowing the combinatorial logic supply voltage to scale for power savings. When compared to a conventional master-slave flip-flop design, the proposed flip-flop design provides up to 80% energy reduction with logic operating at reduced voltage and speed. Fifty-percent energy reduction is obtained without compromising speed when operating with all circuits at maximum voltage.

A High-Efficiency Strongly Self-Checking Asynchronous Datapath

This work examines the inherent self-checking (SC) property of latch-free dynamic asynchronous datapath (LFDAD) using differential cascode voltage switch logic. Consequently, a highly efficient SC dynamic asynchronous datapath architecture is presented. In this architecture, no hardware needs to be added to the datapath to achieve SC. The presented implementation is efficient in terms of speed and area and represents a new approach to fault-tolerant design.

A Low-Latency Asynchronous Shift Register

In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.

An efficient self-timed adder realized using conventional CMOS standard cells

Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 μm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.

Impact of technology scaling on CMOS logic styles

In this paper, the main challenges of technology scaling are reviewed in depth. Five popular logic families namely; conventional CMOS, complementary pass logic, Domino, differential cascode voltage switch logic, and current mode logic are presented, highlighting their advantages and drawbacks. The behavior of each logic style in deep submicrometer technologies is analyzed and predicted for future technology generations. To verify the qualitative analysis, simulations were performed on the basic logic gates, full adder and a 16-bit carry look ahead adder. The circuits were implemented in 0.8-, 0.6-, 0.35-, and 0.25-/spl mu/m CMOS technologies, and optimized for minimum energy-delay product.

Low power DCVSL circuits employing AC power supply

In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cascode voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

A new high-speed domino circuit, called HS-Domino has been developed. HS-Domino resolves the tradeoff between performance and reliability in conventional CD-domino logic while dissipating low dynamic power with minimal area overhead. HS-Domino, therefore, extends domino's operation in the deep submicron regime. A multithreshold implementation of HS-Domino is also devised to achieve substantially low leakage values during standby, while maintaining high performance and low power during the active mode. Furthermore, the generic multithreshold scheme is applied to differential cascode voltage switch (DDCVS) logic.