Different Forms Of Parallelism Research Articles

QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds

Point clouds have been employed extensively in machine perception applications. Farthest point sampling (FPS) is a critical kernel for point cloud processing. With the rapid growth of point cloud scale, FPS introduces a large number of memory accesses, which become the bottleneck of the large-scale point cloud processing. In this paper, we present QuickFPS, an architecture and algorithm co-design of farthest point sampling in large-scale point clouds. First, We systemically analyze the characteristics of FPS and put forward a bucket-based farthest point sampling algorithm. The algorithm introduces a two-level tree data structure to organize the large-scale point cloud into multiple buckets. By using two mechanisms named merged computation and implicit computation for the buckets, the external memory accesses and compute cost are significantly reduced. Then, we design an efficient domain-specific accelerator for farthest point sampling in large-scale point clouds. The accelerator takes advantage of different forms of parallelism and further improves the accelerator’s efficiency. Finally, we evaluate QuickFPS with several widely used point cloud datasets, which include small-scale and large-scale point clouds (up to 120,000 points). Overall, QuickFPS achieves performance speedups of 43.4x and 12.2x compared to GTX 1080Ti GPU and state-of-the-art point cloud accelerator PointAcc, respectively.

An Insufficient Canon: The Popol Wuj, Book of Mormon, and Other Scriptures

An Insufficient Canon: The Popol Wuj, Book of Mormon, and Other Scriptures

Memory-Aware Functional IR for Higher-Level Synthesis of Accelerators

Specialized accelerators deliver orders of a magnitude of higher performance than general-purpose processors. The ever-changing nature of modern workloads is pushing the adoption of Field Programmable Gate Arrays (FPGAs) as the substrate of choice. However, FPGAs are hard to program directly using Hardware Description Languages (HDLs). Even modern high-level HDLs, e.g., Spatial and Chisel, still require hardware expertise. This article adopts functional programming concepts to provide a hardware-agnostic higher-level programming abstraction. During synthesis, these abstractions are mechanically lowered into a functional Intermediate Representation (IR) that defines a specific hardware design point. This novel IR expresses different forms of parallelism and standard memory features such as asynchronous off-chip memories or synchronous on-chip buffers. Exposing such features at the IR level is essential for achieving high performance. The viability of this approach is demonstrated on two stencil computations and by exploring the optimization space of matrix-matrix multiplication. Starting from a high-level representation for these algorithms, our compiler produces low-level VHSIC Hardware Description Language (VHDL) code automatically. Several design points are evaluated on an Intel Arria 10 FPGA, demonstrating the ability of the IR to exploit different hardware features. This article also shows that the designs produced are competitive with highly tuned OpenCL implementations and outperform hardware-agnostic OpenCL code.

LINGUOPOETIC CLASSIFICATION OF PARALLELISM IN AZERBAIJAN AND ENGLISH

The article deals with the ways of classification of linguopoetic features of parallelism in the Azerbaijan and English languages. We present research on the classification of different forms of parallelism in the linguistics and poetry of both languages. So, parallelism in the poetry is firstly used as mnemonic device expressing different feeling then used as a term in linguistics. Its linguopoetic interpretation aids to find out different use, functions and types of parallelism. In the research of parallelism different classifications have been considered by linguistic scholars of both languages and in these classifications the most common types of parallelism and their use have widely been investigated.This article proposes an approach for handling such an issue that has different groups and sub-groups by classifying them into their respective categories based on all various types in both English and Azerbaijani. The collected data is analyzed by a means of quantitative approach. The findings not only facilitate the further understanding of classification of linguopoetic features of parallelism, but also provide learners and readers who engaged in issue with useful clues on types of parallelism they should implement. More importantly, the article is intended to give an insight to the characteristics of various linguopoetic types of parallelism, in order to ease grouping of all types effortlessly and fast.

FPGA-Based Parallel Hardware Architecture for Real-Time Image Classification

This paper proposes a parallel hardware architecture for real-time image classification based on scale-invariant feature transform (SIFT), bag of features (BoFs), and support vector machine (SVM) algorithms. The proposed architecture exploits different forms of parallelism in these algorithms in order to accelerate their execution to achieve real-time performance. Different techniques have been used to parallelize the execution and reduce the hardware resource utilization of the computationally intensive steps in these algorithms. The architecture takes a ${\mathbf {640}} \times {\mathbf {480}}$ pixel image as an input and classifies it based on its content within 33 ms. A prototype of the proposed architecture is implemented on an FPGA platform and evaluated using two benchmark datasets: 1) Caltech-256 and 2) the Belgium Traffic Sign datasets. The architecture is able to detect up to 1270 SIFT features per frame with an increment of 380 extra features from the best recent implementation. We were able to speedup the feature extraction algorithm when compared to an equivalent software implementation by ${\mathbf {54}} \times$ and for classification algorithm by ${\mathbf {6}} \times$ , while maintaining the difference in classification accuracy within 3%. The hardware resources utilized by our architecture were also less than those used by other existing solutions.

PLDS

Recently, parallelization of computations in the presence of dynamic data structures has shown promising potential. In this paper, we present PLDS, a system for easily expressing and efficiently exploiting parallelism in computations that are based on dynamic linked data structures. PLDS improves the execution efficiency by providing support for data partitioning and then distributing computation across threads based on the partitioning. Such computations often require the use of speculation to exploit dynamic parallelism. PLDS supports a conditional speculation mechanism that reduces the cost of speculation. PLDS can be employed in the context of different forms of parallelism, which to cover a wide range of parallel applications. PLDS provides easy-to-use compiler directives, using enabling programmers to choose from among a variety of data partitionings to distribute computation across threads in a partitioning-sensitive fashion, and to use conditional speculation when required. We evaluate our implementation of PLDS using ten benchmarks, of which six are parallelized using speculation. PLDS achieves 1.3x--6.9x speedups on an 8-core machine.

KPN2GPU

With advances in manycore and accelerator architectures, the high performance and embedded spaces are rapidly converging. Emerging architectures feature different forms of parallelism. The Polyhedral Processes Networks (PPNs) are a proven model of choice for automated generation of pipeline and task parallel programs from sequential source code, however data parallelism is not addressed. In this paper, we present asystematic approach for identification and extraction of fine grain data parallelism from the PPN specification. The approach is implemented in a tool, called kpn2gpu, which produces fine-grain data parallel CUDA kernels for graphics processing units (GPUs). First experiments indicate that generated applications have a potential to exploit different forms of parallelism provided by the architecture and that kernels feature a highly regular structure that allows subsequent optimizations.

SpiceC

In this paper we present an approach to parallel programming called SpiceC. SpiceC simplifies the task of parallel programming through a combination of an intuitive computation model and SpiceC directives. The SpiceC parallel computation model consists of multiple threads where every thread has a private space for data and all threads share data via a shared space. Each thread performs computations using its private space thus offering isolation which allows for speculative computations. SpiceC provides easy to use SpiceC compiler directives using which the programmers can express different forms of parallelism. It allows developers to express high level constraints on data transfers between spaces while the tedious task of generating the code for the data transfers is performed by the compiler. SpiceC also supports data transfers involving dynamic data structures without help from developers. SpiceC allows developers to create clusters of data to enable parallel data transfers. SpiceC programs are portable across modern chip multiprocessor based machines that may or may not support cache coherence. We have developed implementations of SpiceC for shared memory systems with and without cache coherence. We evaluate our implementation using seven benchmarks of which four are parallelized speculatively. Our compiler generated implementations achieve speedups ranging from 2x to 18x on a 24 core system.

Exponential expansion for field computation and capacitance extraction

We report a new numerical technique based on the exponential expansion of the Green's function 1/r for accurate and rapid computation of the three-dimensional potential field, its gradient, and the charge density distribution needed for capacitance extraction in multiple-dielectric-multiconductor systems. The exponential expansion provides a computational efficient alternative to the commonly used technique based on multipole expansion of spherical harmonics. With exponential expansion, the memory requirement is independent of the desired degree of accuracy and different forms of parallelism are available for both remotely distributed networks and closely coupled parallel systems. These features permit large-scale simulation, involving panel (element) count in the range of a few hundred thousand to several million, needed for extraction of the parasitic coupling capacitance in VLSI interconnects, including large-area amorphous silicon electronics, as well as for analysis of electrostatic interaction in micro-electro-mechanical systems (MEMS).

Exploiting and-or parallelism in Prolog: The OASys computational model and abstract architecture

Different forms of parallelism have been extensively investigated over the last few years in logic programs and a number of systems have been proposed. Or/And System (OASys) is an experimental parallel Prolog system that exploits and-or-parallelism and comprises a computational model, a compiler, an abstract machine and an emulator. OASys computational model combines the two types of parallelism considering each alternative path as a totally independent computation which consists of a conjunction of determinate subgoals. It is based on distributed scheduling and supports recomputation of paths as well as stack copying. The system features modular design, high distribution and minimal inter-processor communication. This paper presents briefly the computational model and describes the abstract machine discussing data representation, memory organization, instruction set, operation and synchronization. Finally performance results obtained by the single-processor implementation and the multiple-processor emulation are discussed.

A review of exploitation of AND-parallelism and combined AND/OR-parallelism in logic programs

Logic programs provide many opportunities for parallel execution. Among different forms of parallelism found in logic programs, AND-parallelism and OR-parallelism have shown to be most effective in speeding up the execution of logic programs. This paper offers a review of major activities in exploiting AND-parallelism and combined AND/OR-parallelism. Full version of this paper (23 pages) can be retrieved through anonymous ftp from ftp.mpce.mq.edu.au.

Exploiting OR-parallelism in logic programs: A review

Different forms of parallelism have been identified in logic programs for efficient implementations on multiprocessor systems. Among these, OR- and AND-parallelism have been the focus for exploitation for the past decade. Research in such exploitation has led to the proposals and implementations of various execution models and logic programming systems. This paper attempts to summarise, in the form of a structured review, the major activities in the area of exploiting OR-parallelism. Problems arising in implementing OR-parallelism and various models and working systems featuring different techniques for solving these problems are discussed.

Extended parallelism in the Gr�bner basis algorithm

This paper presents a new parallel implementation to compute Grobner bases utilizing two different forms of parallelism. A coarse-grain technique developed by Jean-Phillipe Vidal expands and reducesS-polynomials in parallel. A finegrain technique, proposed by Melenk and Neun, constructs a pipeline of processors to overlap execution of the reduction operations. A hybrid algorithm that outperforms both of the original approaches is presented. The combined algorithm requires the user to select the appropriate allocation of processors to the two styles of parallelism, and uses this static assignment throughout the computation. The paper also discusses the design and implementation approaches used to construct an efficient version of this algorithm.

Architectural requirements of image understanding with respect to parallel processing

An overview of the architectural requirements for parallel processing in support of real-time, knowledge-based computer vision is given. One of the goals of this work is to provide an appreciation for the diversity, complexity, and computational intensity of vision processing. It begins with a description of common vision algorithms, analyzes their requirements in terms of the inherent structures that are present, and relates them to computation, communication, and control in parallel processing. After concluding that traditional architectural approaches to parallel processors are suboptimal, discussion focuses on heterogeneous processors. Different forms of parallelism can be applied at three levels of computational granularity, each having unique requirements and corresponding to levels of abstraction in the image interpretation process. In addition, interaction between levels must take place via parallel data and control paths. The paper concludes with a brief discussion of image understanding architecture, a multilevel parallel processor designed for image understanding.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>