Dielectric Relaxation Current Research Articles

Investigating dielectric relaxation currents for a deeper understanding of capacitance and interface in metal-insulator-metal capacitor

Investigating dielectric relaxation currents for a deeper understanding of capacitance and interface in metal-insulator-metal capacitor

Detection of near-interface traps in NO annealed 4H-SiC metal oxide semiconductor capacitors combining different electrical characterization methods

Fast near-interface (NI) traps have recently been suggested to be the main cause for poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors. Combining capacitance, conductance, and thermal dielectric relaxation current (TDRC) analysis at low temperatures of nitrided SiC MOS capacitors, we observe two categories of fast and slow near-interface traps at the SiO2/4H-SiC interface. TDRC reveals a suppression of slow near-interface traps after nitridation. Capacitance and conductance analysis reveals a high density of fast NI traps close to the SiC conduction band edge that are enhanced by nitridation. The very fast response of NI traps prevents them from detection using TDRC or deep level transient spectroscopy.

Detection and Cryogenic Characterization of Defects at the SiO2/4H-SiC Interface in Trench MOSFET

We employed the thermal dielectric relaxation current (TDRC) method for the detection and cryogenic characterization of traps at the 4H-SiC/SiO2 interface in n-channel trench MOSFETs and n-MOS trench capacitors. The interface of trench devices on the ( $\textsf {11}\overline {2}\textsf {0}$ )-plane atomically differs from the interface of standard lateral devices [(0001)-plane]. In the MOSFET, two TDRC signal peaks originating from electron traps were found and characterized by parameter variation in TDRC measurements. One peak corresponds to interface states located 0.13 eV below the 4H-SiC conduction band edge EC. The other one is attributed to the near-interface traps (NITs) with an electron emission barrier of 0.3 eV. The NIT peak shows an inverse dependence on the discharging voltage compared to regular interface states. In contrast to the MOSFET, only NITs were measured in n-type MOS capacitors. The results found in trench devices were also confirmed for lateral devices. Therefore, we show that the study of SiC MOS capacitors is not sufficient for the understanding of degradation mechanisms in SiC MOSFETs. The interface states at EC-0.13 eV detected in MOSFETs are assumed to contribute to the degradation of the apparent channel mobility and ON-resistance of SiC MOSFETs. These states are strongly reduced by annealing in NO compared to N2.

Determination of Performance-Relevant Trapped Charge in 4H Silicon Carbide MOSFETs

Current-voltage characterization and thermal dielectric relaxation current (TDRC) measurements are carried out on 4H silicon carbide (SiC) n-channel MOSFETs processed with different post oxidation anneals (POAs) in O2, N2O, and NO atmospheres at high temperature. In all samples we observe a distinct peak at a temperature of 70 K in the TDRC spectra due to a defect close to the conduction band of 4H-SiC having a high density of states (>1013 cm-2eV-1). We show that this defect is related to the degradation of the device performance such as the MOSFET conductivity. Comparing the different POAs, NO strongly reduces the density of states close to the conduction band and thus increases the amount of free channel electrons. Based on TDRC measurements we want to suggest a method for more accurate estimation of the true channel mobility accounting for the reduced channel electron density due to trapping.

Relaxation currents in morphotropic region of Pb[(Fe1/3Sb2/3) x Ti y Zr z ]O3 ferroelectric ceramics

Studies on the dielectric relaxation currents in the morphotropic region of Pb[(Fe1/3Sb2/3) x Ti y Zr z ]O3 with x + y + z = 1, x = 0.1 and y = 0.44–0.46 are presented. The measurements have been performed at three poling fields, i.e. (a) 0.02 kV cm−1 that is much lower than the coercive force (8 kV cm−1), (b) 10 kV cm−1, i.e. slightly above the coercive force and (c) much higher field (20 kV cm−1). There were measured transient polarisation and depolarisation currents. For a low poling field, these currents do not differ from each other, but for higher fields the difference increases with increasing poling field. The analysis of depolarisation current data obtained at various temperatures (298–473 K) shows that relaxation time τp varies exponentially with temperature. The activation energies calculated for samples with y = 0.44, 0.45 and 0.46 equals to 0.26, 0.24 and 0.22 eV, respectively. The defect dipole ) complex and the Dissado–Hill double-minimum potential models are proposed to explain the observed relaxation behaviour in Pb[(Fe1/3Sb2/3) x Ti y Zr z ]O3 ferroelectric ceramics.

Study of radiation damage induced by 12 keV X-rays in MOS structures built on high-resistivityn-type silicon

Imaging experiments at the European X-ray Free Electron Laser (XFEL) require silicon pixel sensors with extraordinary performance specifications: doses of up to 1 GGy of 12 keV photons, up to 10(5) 12 keV photons per 200 µm × 200 µm pixel arriving within less than 100 fs, and a time interval between XFEL pulses of 220 ns. To address these challenges, in particular the question of radiation damage, the properties of the SiO(2) layer and of the Si-SiO(2) interface, using MOS (metal-oxide-semiconductor) capacitors manufactured on high-resistivity n-type silicon irradiated to X-ray doses between 10 kGy and 1 GGy, have been studied. Measurements of capacitance/conductance-voltage (C/G-V) at different frequencies, as well as of thermal dielectric relaxation current (TDRC), have been performed. The data can be described by a dose-dependent oxide charge density and three dominant radiation-induced interface states with Gaussian-like energy distributions in the silicon band gap. It is found that the densities of the fixed oxide charges and of the three interface states increase up to dose values of approximately 10 MGy and then saturate or even decrease. The shapes and the frequency dependences of the C/G-V measurements can be quantitatively described by a simple model using the parameters extracted from the TDRC measurements.

Device Performance and Reliability Improvement for MOSFETs With $\hbox{HfO}_{2}$ Gate Dielectrics Fabricated Using Multideposition Room-Temperature Multiannealing

In this letter, a room-temperature multideposition multiannealing (MDMA) technique in ultraviolet ozone (UVO) ambient is applied to metal-gated (TiN) ALD HfO2 gate dielectric. Compared to the conventional rapid thermal annealing, the nMOSFETs with UVO MDMA show superior properties, in terms of enhanced channel electron mobility, improved immunity to biased temperature instability, and reduced gate dielectric relaxation current. This is explained by the reduction of bulk oxide trap and interface trap density because of healing of oxygen vacancies (Vo) after UVO MDMA annealing. The novel room-temperature UVO annealing is thus proposed to be a promising technique to enhance the gate stack integrity in a gate-last integration scheme.

Analysis of electron traps at the 4H–SiC/SiO2 interface; influence by nitrogen implantation prior to wet oxidation

Electron states at the SiO2/4H–SiC interface have been investigated using capacitor structures and especially, the influence of excess nitrogen, introduced by ion implantation, at the interface is studied in detail. Implanted and nonimplanted n-type samples with an interfacial concentration of nitrogen of ∼1019 cm−3 and 1016 cm−3, respectively, were analyzed by capacitance-voltage (C-V) measurements, performed at different temperatures and probe frequencies, and thermal dielectric relaxation current (TDRC) measurements performed in the temperature range of 35–295 K. Three main categories of electron states are disclosed, true interface states (Dit), fast near interface states (NIToxfast) and slow near interface states (NIToxslow). The density versus energy distributions of Dit and NIToxfast have been deduced from the TDRC data and they are shown to give a close quantitative agreement with the shape and frequency dependence of the C-V curves. Further, the amount of NIToxslow extracted from TDRC is demonstrated to be responsible for the parallel shifts and hysterezis effects occurring in the C-V characteristics. All three categories of electron states are reduced in concentration in the implanted samples. This holds particularly for NIToxfast with a peak at ∼0.1 eV below the conduction band edge of 4H–SiC that is suppressed by at least two orders of magnitude relative to the nonimplanted samples. The decrease for Dit is also substantial (a factor of ∼10) while the loss for NIToxslow is considerably smaller (only ∼30%). The results provide firm evidence that NIToxfast and NIToxslow do not originate from the same kind of defect center.

Detection and Electrical Characterization of Defects at the SiO<sub>2</sub>/4H-SiC Interface

Two electrical measurement techniques are frequently employed for the characteri- zation of traps at the SiO2/SiC interface: the thermal dielectric relaxation current (TDRC) and the conductance method (CM). When plotting Dit as a function of the energy position Eit in the bandgap both techniques reveal comparable results for deep interface traps (ECEit > 0:3 eV). For shallower traps, CM always shows a strong increase of Dit which originates from near interface traps (NIT). TDRC provides a contradictory result, namely a slight decrease of Dit. In this paper, we show that the position of NITs in the oxide close to the interface is responsible for the invisibility of these traps in TDRC spectra. We further show that NITs become detectable by the TDRC method by using a discharging voltage Vdis close to the accumulation regime. However, due to the Shockley-Ramo-Theorem the contribution of NITs to the Dit in TDRC spectra is strongly suppressed and can be increased by using thin oxides.

Breakdown phenomena of Al-based high-k dielectric/SiO2 stack on 4H-SiC

In this report we present the breakdown phenomena of Al-based high-k dielectrics and thermal SiO2 intermediate layer stack on 4H-SiC. The Al-based dielectrics, namely, sputter deposited aluminum nitride (AlNx) and hydrogenated aluminum nitride (AlNy:H), have been used to form metal-insulator-semiconductor (MIS) capacitors and field-plate terminated Schottky barrier diodes (SBDs) on 4H-SiC. Multistep breakdown modes visible on these devices have been investigated using measurements of dielectric relaxation currents on MIS capacitors.

Interface States in 4H- and 6H-SiC MOS Capacitors: A Comparative Study between Conductance Spectroscopy and Thermal Dielectric Relaxation Current Technique

The purpose of this work is to compare the density of shallow interface states (Dit) at the interface of SiO2/SiC MOS capacitors as deducted by the conductance spectroscopy (CS) and thermally dielectric relaxation current (TDRC) techniques. Both capacitors of 4H- and 6H-SiC (n-type) are investigated, and both ordinary dry oxidation and an improved industrial procedure have been employed. The two techniques are found to give rather good agreement for interface states located ≥0.3 eV below the conduction band edge (Ec) while for more shallow states vastly different distributions of Dit are obtained. Different reasons for these contradictory results are discussed, such as strong temperature and energy dependence of the capture cross section of the shallow interface states.

The Al<sub>2</sub>O<sub>3</sub>/4H-SiC Interface Investigated by Thermal Dielectric Relaxation Current Technique

Al2O3 has been grown by Atomic Layer Chemical Vapour Deposition (ALCVD) on ntype 4H-SiC using O3 as an oxidant and tri-methyl-aluminum (TMA) as a precursor. After deposition, annealing at 1000°C during 3h in different atmospheres (Ar, N2 and O2) was performed. Interface properties were studied by Capacitance-Voltage (CV) and Thermal Dielectric Relaxation Current (TDRC) measurements. The highest near-interface trap density (Nit) was deduced to be 4x1012 eV-1cm-2 between 0.36 eV and 0.5 eV below the conduction band, Ec, for O2 annealed samples, 2.8x1012 eV-1cm-2 between 0.42 eV and 0.56 eV below Ec for Ar annealed samples and 2.2x1012 eV-1cm-2 between 0.4 eV and 0.6 eV below Ec for N2 annealed samples. Only samples annealed in Ar exhibit a nearly trap free region close to Ec. Annealing in N2 is found to decrease Nit between 0.3 and 0.7 eV but shows a slightly higher Nit close the conduction band compared to the Ar case.

Electrical properties of Al2O3∕4H-SiC structures grown by atomic layer chemical vapor deposition

Al 2 O 3 films have been deposited on n-type and p-type 4H-SiC by atomic layer chemical vapor deposition using trimethylaluminum as a precursor for aluminum and both H2O and O3 as an oxidant. After oxide deposition, annealing at different temperatures (800, 900, 1000°C) in argon atmosphere for different durations (1, 2, 3h) was performed. Bulk and interface properties of the oxide films were studied by capacitance-voltage, current-voltage, deep level transient spectroscopy, and thermally dielectric relaxation current (TDRC) measurements. The results reveal a decreasing flatband voltage with increasing annealing time, suggesting decrease of oxide charges and deep interface traps. After 3h annealing at 1000°C of the n-type samples, the flatband voltage is reduced to 6V compared to a value in excess of 40V for as-deposited samples. The TDRC measurements on annealed Al2O3∕SiC (n-type) capacitors showed substantially different spectra relative to conventional SiO2∕4H-SiC control samples; in the former ones no signal was recorded at temperatures less than 100K, demonstrating a low density of shallow electron traps below the conduction band edge of 4H-SiC and hence a prospect of obtaining a high electron channel mobility in 4H-SiC metal-oxide-semiconductor field-effect devices with Al2O3 as gate dielectric.

Modification of Trap Distributions in Anodic Aluminum Tunnel Barriers

The trap distribution in thin aluminum oxide films was modified electrochemically and subsequently quantified in a solid-state device. A combined potentiodynamic/potentiostatic experiment enabled preparation of samples showing different trap distributions with negligible thickness variation. Potentiodynamic oxide formation at a scan rate of was used to form the anodic oxide with many defects. Subsequent potentiostatic polarization allowed a systematic reduction of the number of defects by electromigrative annealing. These oxides were used as a dielectric barrier in a metal-insulator-metal multilayer system with a silver top electrode. The current response of these samples to voltage pulses was investigated over a wide range in current and time . A separation of Debye charging, dielectric relaxation, and steady-state tunnel current was possible in the time domain. The dielectric relaxation showed a very strong dependence on the previous electromigrative annealing time being approximately 85 times higher for a short annealing time of as compared to the longest annealing time of . The steady-state tunnel current displayed a much weaker dependence of only a factor of 1.6 and changed mainly during the initial annealing step from . In this way it is possible to prepare anodic oxide films of constant film thickness with variable trap site densities. These films have identical tunneling properties but display extremely different relaxation behaviors.

Comparison between oxidation processes used to obtain the high inversion channel mobility in 4H-SiC MOSFETs

In this work two oxidation methods aimed at improving the silicon face 4H-SiC/SiO2 interface are compared. One is an oxidation in N2O performed in a quartz tube using quartz sample holders and the other is a dry oxidation performed in an alumina tube using alumina sample holders. In n-type metal oxide semiconductor (MOS) capacitors the interface state density near the SiC conduction band edge is estimated using capacitance–voltage (C–V) and thermal dielectric relaxation current (TDRC) measurements. N-channel metal oxide semiconductor field effect transistors (MOSFETs) are characterized by current–voltage (I–V) techniques and the inversion channel mobility is extracted. It is shown that the high inversion channel mobility (154 cm2 V−1 s−1) seen in samples oxidized using alumina correlates with a low interface trap density (3.6 × 1011 cm−2). In the case of N2O oxidation the mobility is lower (24 cm2 V−1 s−1) and the interface trap density is higher (1.6 × 1012 cm−2). Room temperature C–V measurements are of limited use when studying traps near the conduction band edge in MOS structures while the TDRC measurement technique gives a better estimate of their density.

Charge Trapping in High-$k$Gate Stacks Due to the Bilayer Structure Itself

Charge trapping at the interface between the two dielectric layers of a high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k$</tex> gate stack is shown to be caused by Maxwell–Wagner instability, which is the following. The fact that the high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k$</tex> and interfacial layers have different compositions means that they will also have different conductivities. Then, a gate bias will produce a discontinuity in current at their interface, causing charge to accumulate there until, in steady state, the same current flows through both layers. Maxwell–Wagner instability is shown to be coupled to a second instability, dielectric relaxation of the high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k$</tex> layer; continuity of current in steady state requires that the electric fields in the two dielectric layers remain fixed, so the change in polarization of the high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k$</tex> layer due to dielectric relaxation must be compensated for by the conduction of additional charge to the interface. Evidence for this behavior in high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k$</tex> gate stacks is found in the thickness dependence of their dielectric relaxation current, with the correct dependence being obtained only from a model in which the two instabilities act simultaneously. Uniform dielectrics do not exhibit Maxwell–Wagner instability, and perfect crystals do not exhibit dielectric relaxation, making the ideal high- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$k$</tex> gate dielectric a uniform single-layer perfect crystal bonded epitaxially to the Si substrate.

A study of thermally stimulated dielectric relaxation currents in Al/Lu 2O 3/Al thin-film sandwiches

Results of experimental examinations of thermally stimulated dielectric relaxation currents (TSDRC) for lutetium oxide films in metal/insulator/metal (MIM) structures have been presented. Al/Lu 2O 3/Al thin-film devices (sandwich-type structures) were prepared on silica plates by physical vapour deposition. Lu 2O 3 films were fabricated by reactive deposition in oxygen with the help of an electron gun. The TSDRC curves measured in the temperature range from 297 K to 500 K were characterized by a single peak connected with trapping centers with the energy depth of 0.81 eV. The influence of the polarization voltage and polarization time on the TSDRC spectra was tested. The charge released during the relaxation process was estimated and analyzed. The TSDRC spectra were analyzed taking into account two Schottky barriers at each M/I electrode. A transition between barrier-processes and volume-processes has been observed.

Interfaces between 4H-SiC and SiO2: Microstructure, nanochemistry, and near-interface traps

We report on electrical and microscopic investigations aimed to clarify the origin of near-interface traps (NITs) in metal–silicon dioxide–4H-silicon carbide structures. Using capacitance–voltage and thermal dielectric relaxation current (TDRC) analysis we investigated NITs close to the 4H-SiC conduction-band edge in differently prepared thermal and deposited oxides and found that the traps give rise to two characteristic TDRC signatures belonging to two groups of trap levels. The total trapped charge exceeds 1×1013cm−2. The observed density and energy distribution of these traps are nearly identical in all thermal and deposited oxides investigated, suggesting that the NITs belong to intrinsic defects at the SiO2∕SiC interface which are readily formed during oxide deposition or thermal oxidation of 4H-SiC. Using high-resolution electron microscopy combined with nanochemical analysis (electron energy-loss near-edge spectroscopy and energy-filtered transmission electron microscopy) we investigated the SiO2∕SiC interface in samples receiving reoxidation and did not find any indication of graphitic regions at or near the SiO2∕SiC interface or in the bulk silicon dioxide within a detection limit of 0.7nm. In addition, no amorphous carbon accumulation was observed near the SiO2∕SiC interface. The overall results strongly suggest that the NITs near the 4H-SiC conduction band are not related to carbon structures in the SiO2∕SiC interlayer.

Influence of Bottom Electrodes and Interface Layers on (Ba,Sr)TiO3 Thin Film Leakage Current

The effect of bottom electrodes of (Ba,Sr)TiO3 (BST) thin film capacitors on leakage current characteristics was investigated. Iridium (Ir), titanium (Ti) and tantalum (Ta) bottom electrodes and SiN interface layer were deposited prior to BST deposition. On the basis of time-dependent and temperature-dependent leakage current characteristics, the leakage mechanism was investigated. It is found that the leakage current in BST with the Ta bottom electrode (Ir/BST/Ta/Si) is dominated by dielectric relaxation current due to the existence of thick TaOx. Leakage currents in BST with the Ir bottom electrode (Ir/BST/IrOx/Ir/Si) and BST on Si substrate (Ir/BST/SiO2/Si) were determined by dielectric relaxation characteristics at low electric field and by Poole–Frenkel emission at high electric field. The leakage current in BST with the Ti bottom electrode (Ir/BST/Ti/Si) was dominated by Poole–Frenkel emission at the range of applied field.

Double-well model of dielectric relaxation current

We show that a straightforward account of dielectric relaxation current in glasses follows from a semiclassical treatment of the double-well model [P. W. Anderson, B. I. Halperin, and C. M. Varma, Philos. Mag. 25, 1 (1972) and W. A. Phillips, J. Low Temp. Phys. 7, 351 (1972)] explaining the linear specific heat of glasses at low temperature. The current is obtained from the field-induced tunneling of the glass between the minima of its potential energy surface, and is found to have the experimentally observed linear dependence on field and inverse dependence on time. The effects of temperature and prior biases are briefly discussed, as well as the relation of the model to the theory of charge trapping. No dielectric relaxation is expected in a perfect insulating crystal, raising the important technological question of how perfect high-k dielectrics like HfO2 and ZrO2 must be in order to serve as gate dielectrics in transistors.