Dielectric Constant Oxide Research Articles

Critical investigation of high performance spin-coated high-κ titania thin films based MOS capacitor

We report the tunable dielectric constant of titania films with low leakage current density. Titanium dioxide (TiO2) films of three different thicknesses (36, 63 and 91 nm) were deposited by the consecutive steps of solution preparation, spin-coating, drying, and firing at different temperatures. The problem of poor adhesion between Si substrate and TiO2 insulating layer was resolved by using the plasma activation process. The surface roughness was found to increase with increasing thickness and annealing temperature. The electrical investigation was carried out using metal-oxide-semiconductor structure. The flat band voltage (VFB), oxide trapped charge (Qot), dielectric constant (κ) and equivalent oxide thicknesses are calculated from capacitance–voltage (C–V) curves. The C–V characteristics indicate a thickness dependent dielectric constant. The dielectric constant increases from 31 to 78 as thickness increases from 36 to 91 nm. In addition to that the dielectric constant was found to be annealing temperature and frequency dependent. The films having thickness 91 nm and annealed at 600 °C shows the low leakage current density. Our study provides a broad insight of the processing parameters towards the use of titania as high-κ insulating layer, which might be useful in Si and polymer based flexible devices.

Temperature Effect of CNTFET under Different Dielectric Materials

A thorough study of the ballistic effect on the performance of the carbon nanotube field effect transistor has been explored in detail in this paper. The behavior of CNTFETs has been analyzed as a function of temperature by varying the gate dielectric constant and gate oxide thickness. Current ratio with a fixed oxide thickness and diameteris observed under different temperature for different dielectric materials and the ratio is increased while increasing the dielectric constant but the ratio degrades with the increasing temperature for all dielectric materials. On the other hand, current ratio is decreased while increasing oxide thickness for a fixed dielectric material and diameter as a function of temperature. The degradation of current ratio in lower temperature range is noticeable but for higher temperature range the slope of the degradation of current ratio is almost constant. The off state current remains same regardless of varying dielectric constant and oxide thickness and always increases while increasing the temperature. Transconductance remains almost constant as a function of temperature but increases with the increase of dielectric constant for all oxide thickness for a fixed tube diameter. Transconductance slightly decreases with the increasing oxide thickness for all dielectric materials. Effect of tube diameter for the variation of band gap is also investigated which is inverse relationship.

Impact of Native Defects in the High Dielectric Constant Oxide HfSiO4 on MOS Device Performance**Supported by the Science Foundation from Education Department of Liaoning Province under Grant No L2014445.

Native defects in HfSiO4 are investigated by first principles calculations. Transition levels of native defects can be accurately described by employing the nonlocal HSE06 hybrid functional. This methodology overcomes the band gap problem in traditional functionals. By band alignments among the Si, GaAs and HfSiO4, we are able to determine the position of defect levels in Si and GaAs relative to the HfSiO4 band gap. We evaluate the possibility of these defects acting as fixed charge. Native defects lead to the change of valence and conduction band offsets. Gate leakage current is evaluated by the band offset. In addition, we also investigate diffusions of native defects, and discuss how they affect the MOS device performance.

Effects of post deposition annealing, interface states and series resistance on electrical characteristics of HfO2 MOS capacitors

The purposes of this paper are to investigate the post deposition annealing (PDA) effect on structural and electrical characterizations of HfO2 MOS capacitor and the frequency dependency of series resistance and interface states in this device. PDA processes on the HfO2 films deposited using RF magnetron sputtering system were performed in N2 ambient at 350, 550, 650, and 750 °C. The phase identifications and crystallization degrees of the HfO2 films were determined by using X-ray diffractometry. The grain size of the films was varied from 4.5 to 15.23 with increasing in PDA temperature. The HfO2 MOS capacitors were fabricated using the as-deposited and annealed films for electrical characterization. C–V and G/ω–V measurements were performed at 1 MHz frequency. The C–V characteristics of the MOS capacitor fabricated with film annealed at 550 °C show a better behaviour in terms of the high dielectric constant and low effective oxide charge compared to others. For this device, C–V and G/ω–V measurements were performed in different frequencies ranging from 10 kHz to 1 MHz at room temperature. Obtained results show that series resistance and interface states strongly influence the C–V and G/ω–V behaviour of the MOS capacitor.

Electrical Analysis of High Dielectric Constant Insulator and Metal Gate Metal Oxide Semiconductor Capacitors on Flexible Bulk Mono-Crystalline Silicon

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin $(25~\mu{\rm m})$ silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage $({\rm V}_{\rm ramp})$ breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer.

Dependence of memory characteristics on the (ZrO2)x(SiO2)1−x elemental composition for charge trap flash memory applications

Charge trap flash memory capacitors incorporating various (ZrO2)x(SiO2)1−x films (x = 1.0, 0.92, 0.79, 0.63, 0.46, 0.28, 0.17 and 0.08) as the charge trapping layer were fabricated, and the dependence of the memory window, data retention and program/erase speed on the mole fraction value x were investigated. It was observed that changing the elemental composition affects the dielectric constant and equivalent oxide thickness of (ZrO2)x(SiO2)1−x films, and the memory capacitor (x = 0.63) exhibits a memory window as large as 10.7 V for a ±10 V sweeping voltage range, and a low extrapolated charge loss of 9.0% over a period of 10 years. A faster program/erase speed can be obtained for memory capacitors when x = 0.79 and 0.63. The results should be attributed to the different (ZrO2)x(SiO2)1−x microstructures, defect state densities and energy band alignments resulting from the change of compositions. In order to achieve the trade-off between the memory window, data retention, and program/erase speed, the optimal x values of the (ZrO2)x(SiO2)1−x trapping layer are in the range of 0.63 to 0.79 for charge trap flash memory applications. The present study provides useful insights for the composition selection for a complex oxide-based charge trap flash memory.

Synthesis and characterization of high dielectric nano zirconium oxide

High dielectric constant nano zirconium oxide (ZrO2) powder has been synthesized through a hydrothermal technique. The structural characterization of prepared sample was obtained by X-ray diffraction and showed mixed phase (orthorhombic and monoclinic). Further, the surface morphology of synthesized nano zirconium oxide (zirconia) was obtained by scanning electron microscopy (SEM). The frequency dependence of dielectric constant, dielectric loss and impedance of the sample was investigated at room temperature. Our result shows that, the dielectric constant of prepared sample is about 24 at 106Hz frequency and the obtained value was approximately 3 times more than the dielectric constant of commercially available zirconium oxide.

Myoblast differentiation of human mesenchymal stem cells on graphene oxide and electrospun graphene oxide–polymer composite fibrous meshes: importance of graphene oxide conductivity and dielectric constant on their biocompatibility

Recently graphene and graphene based composites are emerging as better materials to fabricate scaffolds. Addition of graphene oxide (GO) nanoplatelets (GOnPs) in bioactive polymers was found to enhance its conductivity (σ) and, dielectric permittivity (ϵ) along with biocompatibility. In this paper, human cord blood derived mesenchymal stem cells (CB-hMSCs) were differentiated to skeletal muscle cells (hSkMCs) on spin coated thin GO sheets composed of GOnPs and on electrospun fibrous meshes of GO–PCL (poly-caprolactone) composite. Both substrates exhibited excellent myoblast differentiations and promoted self-alignedmyotubesformation similar to natural orientation. σ, ϵ, microstructural and vibration spectroscopic studies were carried out for the characterizations of GO sheet and the composite scaffolds. Significantly enhanced values of both σ and ϵ of the GO–PCL composite were considered to provide favourable cues for the formation of superior multinucleated myotubes on the electrospun meshes compared to those on thin GO sheets. The present results demonstrated that both substrates might be used as potential candidates for CB-hMSCs differentiation and proliferation for human skeletal muscle tissue regeneration.

English

A detailed review on the Carbon Nanotube Filed Effect Transistors (CNTFETs) has been given. A little description about what are carbon nanotubes is also been covered. Various simulation results have also been included in this paper in order to provide better understanding about the carbon nanotubes field effect transistors.Characteristic Graphs of a C-CNTFET with n=10. m=11 (diameter=1.4246 nm) have been studied. Threshold voltage of CNTFETs vs n (for m=0) is also simulated. Equivalent high-frequency small-signal circuit model for a Nanotube transistor has also been analyzed. Also current voltage relationship of the CNTFET with respect to gate oxide thickness and dielectric constant has been analyzed.

Ab initio calculation of band alignment of epitaxial La<sub>2</sub>O<sub>3</sub> on Si(111) substrate

By means of plane wave pseudopotential method we have studied the electronic properties of the heterostructure formed by an high dielectric constant (k) oxide, the hexagonal La2O3 epitaxially grown with (0001)-orientation on Si (111) substrate. We found that for La2O3 both the dielectric constant along the growth direction and the band gap are larger in the epitaxial film than in the bulk. By super-cell techniques we have computed the band alignment of the junction finding a valence band offset and a conduction band offset of ~1.6 eV and ~1.7 eV respectively. We demonstrate that the band alignment can be engineered by δ-doping the interface: our simulations show that, by doping the interface with S or Se monolayer, the valence (conduction) band offset increases (decreases) of about 0.5 eV without the formation of spurious electronic states in the semiconductor band-gap. The simulation of the critical thickness of pseudomorphic Lanthana film complete the work. Our results are relevant for the realization of a new generation of devices based on ultra-scaled complementary metal oxides semiconductors (CMOS) technology.

Stacked Dual Oxide Nano MOS Parameter Optimization For 3-D IC Realization

With advent of nano technology, a threshold voltage of a MOSFET can be engineered. In order to increase the packing density of the transistors on multicore processor/SOC with FPGA and processor, and 3-D IC realization, stacking of materials are necessary with lesser parasites like capacitance, voltage drop etc. In this paper, we present Silicon as a base material and metal like TiN (Titanium Nitride) as top layer is analyzed. The parameters of the different stacked materials are optimized to achieve required CStack (Stack Capacitance) and VTh. It is used explore the behavior of dual oxide MOS parameters like oxide material, electron affinity, bandgap, dielectric constant, and thickness.

Effect of thermal annealing and oxygen partial pressure on the swelling of HfO2/SiO2/Si metal-oxide-semiconductor structure grown by rf sputtering: A synchrotron x-ray reflectivity study

As-grown and rapid thermal annealed thin HfO2 films, deposited on Si(100) substrate by reactive rf sputtering at various partial pressures of O2 and Ar, are studied by synchrotron x-ray reflectivity. The growth of interfacial layer (IL) of SiO2 is more or less linear with the decrease in oxygen partial pressure (pO2) in the O2/Ar mixture. The thickest oxide is found to be grown at the minimum oxygen partial pressure (pO2). It is observed that the IL swells upon annealing at higher temperature, and swelling is maximum for the sample grown in minimum pO2. The surface roughness and thickness of the HfO2 films decrease upon annealing indicating a denser film. The HfO2/Si interface roughness is also decreased upon annealing. Therefore, lower annealing temperature and higher pO2 is to be set to reduce the IL thickness and for higher dielectric constant and larger oxide capacitance. High frequency capacitance-voltage (C–V) measurement on the devices, annealed at higher temperature, further shows the necessity for optimization of pO2 during the deposition of HfO2 film to minimize the fixed oxide charge density of metal-oxide-semiconductor devices.

Impact of Q-Time on the Passivation of Al2O3/p-In0.53Ga0.47As Interfaces Using Various Surface Treatments

The downscaling of complementary metal-oxide-semiconductor (CMOS)mayneedtheintegrationofIII-Vsemiconductorsandrelated high-k materials, since Si-based devices have reached their physical limitations. Unfortunately, the inherent poor interfacial quality of IIIV substrates and high dielectric constant gate oxides lead to the large defect state densities (Dit) which results in Fermi level pinning and the loss of channel controlling. 1,2 This issue is still a major challenge that needs to be addressed in spite of many achievements in interface passivation treatments. 3‐12 Recently, either ex-situ chemical and in-situ ALD surface treatments of the In0.53Ga0.47As substrates exhibited the strong minority carrier response at inversion region, which means Fermi level can be freely swept through the bandgap of III/V semiconductor. 9‐11 Similarly, O’Connor et al. 12 achieved the strong inversion behavior for n, p-In0.53Ga0.47As substrates with sulfur treatment and ALD-Al2O3 deposition. They also emphasized the impact of the delay time between the ex-situ chemical surface treatment and the ALD chamber loading (Q-time) on the quality of the high-k/III-V interface. The Q-time should be limited as low as possible; otherwise, the interfacial quality of high-k/III-V will be degraded. In this study, p-In0.53Ga0.47As substrates were treated by several chemical solutions with different Q-times prior to ALD chamber loading. Yet the nice C-V response was still observed even after 24 hours of Q-time for the MOSCAP structures studied. In terms of Q-time property, our results have supported the conclusion which might stand in contrast with previous studies, 7,8,12 i.e., reduced transfer time (less than few minutes) is not necessarily a prerequisite for an efficient chemical passivation of Al2O3/In0.53Ga0.47As interfaces. The nature of interface trap states discussed in this work would facilitate further understanding and passivating of high-k/III-V interfaces.

A 2-D Analytical Model for Double-Gate Tunnel FETs

This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.

High dielectric constant nickel-doped titanium oxide films prepared by liquid-phase deposition

The electrical characteristics of nickel-doped titanium oxide films prepared by liquid-phase deposition on p-type (100) silicon substrate were investigated. The aqueous solutions of ammonium hexafluorotitanate and boric acid were used as precursors for the growth of titanium oxide films and the dielectric constant is 29. The dielectric constant can be improved to 94 by nickel doping at the thermal annealing at 700 °C in nitrous oxide.

Characterization of very low thermal conductivity thin films

Characterization of thermal transport in nanoscale thin films with very low thermal conductivity (<1 W m−1 K−1) is challenging due to the difficulties in accurately measuring spatial variations in temperature field as well as the heat losses. In this paper, we present a new experimental technique involving freestanding nanofabricated specimens that are anchored at the ends, while the entire chip is heated by a macroscopic heater. The unique aspect of this technique is to remove uncertainty in measurement of convective heat transfer, which can be of the same magnitude as through the specimen in a low conductivity material. Spatial mapping of temperature field as well as the natural convective heat transfer coefficient allows us to calculate the thermal conductivity of the specimen using an energy balance modeling approach. The technique is demonstrated on thermally grown silicon oxide and low dielectric constant carbon-doped oxide films. The thermal conductivity of 400 nm silicon dioxide films was found to be 1.2 W m−1 K−1, and is in good agreement with the literature. Experimental results for 200 nm thin low dielectric constant oxide films demonstrate that the model is also capable of accurately determining the thermal conductivity for materials with values <1 W m−1 K−1.

Band offsets, Schottky barrier heights, and their effects on electronic devices

The authors review the band line-ups and band offsets between semiconductors, dielectrics, and metals,including the theory, experimental data, and the chemical trends. Band offsets have been critical in the choice of high dielectric constant oxides to be used in advanced metal oxide semiconductor field effect transistors. It turns out that band offsets are also critical in the theory of doping limits, design of transparent conducting oxides, organic semiconductors, and electrodes to use in light emitting devices, photovoltaic cells, and photochemical cells. It is shown how band line-ups can be understood in terms of charge neutrality levels. These are also related to states due to interstitial hydrogen.

Selective Sodium Sensing with Gold-Coated Silicon Nanowire Field-Effect Transistors in a Differential Setup

Ion-sensitive field-effect transistors based on silicon nanowires with high dielectric constant gate oxide layers (e.g., Al2O3 or HfO2) display hydroxyl groups which are known to be sensitive to pH variations but also to other ions present in the electrolyte at high concentration. This intrinsically nonselective sensitivity of the oxide surface greatly complicates the selective sensing of ionic species other than protons. Here, we modify individual nanowires with thin gold films as a novel approach to surface functionalization for the detection of specific analytes. We demonstrate sodium ion (Na(+)) sensing by a self-assembled monolayer (SAM) of thiol-modified crown ethers in a differential measurement setup. A selective Na(+) response of ≈-44 mV per decade in a NaCl solution is achieved and tested in the presence of protons (H(+)), potassium (K(+)), and chloride (Cl(-)) ions, by measuring the difference between a nanowire with a gold surface functionalized by the SAM (active) and a nanowire with a bare gold surface (control). We find that the functional SAM does not affect the unspecific response of gold to pH and background ionic species. This represents a clear advantage of gold compared to oxide surfaces and makes it an ideal candidate for differential measurements.

First principles study on InP (001)-(2 × 4) surface oxidation

A theoretical study of the oxidation of InP(001)-(2 × 4) surface is performed using density functional theory methods. Our results on surface oxidation show that the oxygen adsorption does not produce any gap states in the bulk InP band gap, due to the saturation of surface In dangling bonds, whereas substitutional oxygen atoms produce gap states. This study also shows that the surface stability increases with the oxygen content, indicating a strong tendency for surface oxidation. Our results help to clarify the origin of surface gap states upon surface oxidation and provide an insight at the atomic level the mechanism of surface oxidation, which will assist in the understanding of the degradation of III-V devices upon oxygen exposure or interfacial oxidation with high dielectric constant oxides.

High‐density remote plasma sputtering of high‐dielectric‐constant amorphous hafnium oxide films

Abstractmagnified imageHafnium oxide (HfOx) is a high dielectric constant (k) oxide which has been identified as being suitable for use as the gate dielectric in thin film transistors (TFTs). Amorphous materials are preferred for a gate dielectric, but it has been an ongoing challenge to produce amorphous HfOx while maintaining a high dielectric constant. A technique called high target utilization sputtering (HiTUS) is demonstrated to be capable of depositing high‐k amorphous HfOx thin films at room temperature. The plasma is generated in a remote chamber, allowing higher rate deposition of films with minimal ion damage. Compared to a conventional sputtering system, the HiTUS technique allows finer control of the thin film microstructure. Using a conventional reactive rf magnetron sputtering technique, monoclinic nanocrystalline HfOx thin films have been deposited at a rate of ∼1.6 nm min−1 at room temperature, with a resistivity of 1013 Ω cm, a breakdown strength of 3.5 MV cm−1 and a dielectric constant of ∼18.2. By comparison, using the HiTUS process, amorphous HfOx (x = 2.1) thin films which appear to have a cubic‐like short‐range order have been deposited at a high deposition rate of ∼25 nm min−1 with a high resistivity of 1014 Ω cm, a breakdown strength of 3 MV cm−1 and a high dielectric constant of ∼30. Two key conditions must be satisfied in the HiTUS system for high‐k HfOx to be produced. Firstly, the correct oxygen flow rate is required for a given sputtering rate from the metallic target. Secondly, there must be an absence of energetic oxygen ion bombardment to maintain an amorphous microstructure and a high flux of medium energy species emitted from the metallic sputtering target to induce a cubic‐like short range order. This HfOx is very attractive as a dielectric material for large‐area electronic applications on flexible substrates.