Dielectric Breakdown Reliability Research Articles

A new empirical extrapolation method for time-dependent dielectric breakdown reliability projections of thin SiO 2 and nitride–oxide dielectrics

The results of an investigation of time-dependent dielectric breakdown (TDDB) of thin gate oxide and nitride–oxide (N–O) films are presented for a wide range of fields and temperatures. It was found that TDDB of both gate oxide and N–O films followed a power-law dependence of mean value ( I avg ) of average leakage current ( I avg). An empirical extrapolation model using average leakage current as a major parameter was proposed based on experimental results. This proposed ( I avg ) lifetime model has been successful to predict dielectric reliability. It could continuously fit the entire breakdown data from both wafer level and module level stress. The extrapolation from wafer level data to module data was excellent. The power of current versus TDDB showed exponential dependence on oxide thickness. This proposed TDDB projection methodology also worked for N–O films with an abrupt current increase in the I– V curve at a certain voltage well below the breakdown voltage, while the conventional models clearly failed to fit all data from this region. The observation of TDDB dependence of the current may open a new window for oxide lifetime projections and provide some insights into the nature of oxide breakdown and its implications for reliability studies.

Study on ZrO2 Deposited Directly on Si as an Alternative Gate Dielectric Material

AbstractReactive-magnetron-sputtered ZrO2 thin film has been deposited on Si directly for gate dielectric application. Both structural and electrical properties of the ZrO2 film have been investigated. An amorphous structure for 30Å ZrO2 and a semi-amorphous structure for 200Å ZrO2 have been revealed. The sputtered film shows a good stoichiometry and a good structural stability of ZrO2 based on the X-ray photoelectron spectroscopy and Rutherford backscattering spectroscopy data. Thin equivalent oxide thickness of about 11.5Å was obtained without the consideration of quantum mechanical effects. A low leakage of less than 10−2 A/cm2 at ±1V relative to the flat band voltage was obtained for this 11.5Å equivalent oxide thickness Pt/ZrO2/Si structure. High effective dielectric breakdown and superior reliability properties have been demonstrated for ZrO2 gate dielectric.

Scalability of Gate/N- Overlapped Lightly Doped Drain in Deep-Submicrometer Regime

In this paper an experimental study of the scalability of a gate/N- overlapped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 µm. The allowable power supply voltage is obtained by investigating the time-dependent dielectric breakdown reliability, the minimum operating voltage, the gate-induced-drain-leakage current, the drain-induced-barrier-lowering effect and the DC hot carrier reliability. It was found that the maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a single drain (SD) structure when VDmax is applied as a supply voltage. The OL-LDD structure has a smaller CGD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with smaller LG. Consequently, the performance of complementary metal-oxide-semiconductor (CMOS) devices with the OL-LDD structure is superior to that with the SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 µm CMOS devices.

Leakage current reduction in chemical-vapor-deposited Ta2O5 films by rapid thermal annealing in N2O

This study aims to improve the electrical characteristics and reliability of low-pressure chemical vapor deposited (LPCVD) Ta/sub 2/O/sub 5/, films by developing a new post-deposition single-step annealing technique. Experimental results indicate that excited oxygen atoms generated by N/sub 2/O decomposition can effectively repair the oxygen vacancies in the as-deposited CVD Ta/sub 2/O/sub 5/ film, thereby resulting in a remarkable reduction of the film's leakage current. Two other post-deposition annealing conditions are compared: rapid thermal O/sub 2/ annealing and furnace dry-O/sub 2/ annealing. The comparison reveals that RTN/sub 2/O annealing has the lowest leakage current, superior thermal stability of electrical characteristics and the best time-dependent dielectric breakdown (TDDB) reliability.

The Dielectric Breakdown Characteristics of Thin Silicon Dioxide Prepared by trans‐1,2‐Dichloroethylene Added Oxidation

The dielectric breakdown characteristics of thin gate oxide prepared by trans 1,2‐dichloroethylene added oxidation as a substitution for 1,1,1‐trichloroethane have been investigated. The t‐DCE was shown to have lower ozone depletion potential than the 1,1,1‐TCA and allows easy replacement of the 1,1,1‐TCA. The interface characteristics were superior or comparable to the conventional pyrogenic oxidation. The dielectric breakdown reliability was improved by addition of t‐DCE. The optimum t‐DCE concentration depends on preoxidation cleaning condition. In the case of the and subsequent DHF preoxidation cleaning, the optimum t‐DCE concentration is 5 weight percent (w/o). In the case of the SC1 preoxidation cleaning, the best dielectric characteristics are shown at higher t‐DCE concentration; however, the recommended t‐DCE concentration is 5 w/o from the view point of balance of cost and performance. The high quality and highly reliable oxide film can be successfully formed by t‐DCE added oxidation, which also minimizes the ozone layer influence. The t‐DCE is a primary candidate to replace the 1,1,1‐TCA.

The Influence of Medium Dose Ion Implantation on the Reliability of Thin Gate Oxide

The influence of medium dose ion implantation on the dielectric breakdown reliability of thin gate oxide is discussed. Medium dose ion implantation and subsequent high temperature oxidation degrade the dielectric breakdown characteristics of metal oxide semiconductor capacitors. The deterioration of breakdown characteristics strongly depends on ion species, dose, oxidation temperature, and oxidation ambient. The dielectric breakdown fields and charge to breakdown reduce drastically at doses of for the arsenic (As+), phosphorus (P+), and boron (B+) implantation, respectively. The breakdowns occur due to weak spots formed along the localized oxidation of silicon (LOCOS) edge by the combination of medium dose ion implantation, high temperature oxidation, and residual stress near the LOCOS edge.

The Reliability Evaluation of Thin Silicon Dioxide Using the Stepped Current TDDB Technique

A wafer level dielectric breakdown reliability measurement technique using logarithmically stepped‐up stress current density is proposed, and the effectiveness of this technique is demonstrated. The stepped current time‐dependent dielectric breakdown (SCTDDB) measurement starts at a very low stress current density , and it steps up logarithmically to a maximum stress current density until oxide breakdown occurs. The SCTDDB measurement has high detection sensitivity for defect‐related breakdown, a wide dynamic range , adequate measurement time (within ), and data compatibility with conventional constant current TDDB result. The SCTDDB technique is a very simple and powerful evaluation tool for thin silicon dioxide reliability analysis.

A sublithographic antifuse structure for field-programmable gate array applications

The authors demonstrate an antifuse structure with a cell area of 0.2*0.2 mu m/sup 2/ which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2- mu m lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse. >

Reliability Degradation Mechanism of Ultrathin Tunneling Oxide by Postannealing

The effect of postoxidation annealing of ultrathin silicon dioxide metal oxide semiconductor capacitors on time dependent dielectric breakdown (TDDB), charge to breakdown , and oxide microstructure, as viewed by transmission electron microscopy, has been examined. The high temperature postannealing degrades the TDDB characteristics of ultrathin oxides with polysilicon gates. The charge to breakdown is reduced drastically with increasing annealing temperature and annealing time. The dielectric breakdown reliability degradation due to postannealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/oxide interface. This increase in roughness is due to grain growth of polysilicon gates and viscous flow of the oxide, which are enhanced with increasing annealing temperature and time.

Post-Annealing Effect on the Reliability of Ultra-Thin Silicon Dioxide with Polysilicon Gate

AbstractTime dependent dielectric breakdown (TDDB) characteristics and TEM observation of ultra-thin silicon dioxide with the polysilicon gate after post-annealing and oxidation at 1000-1100 °C are discussed. The high temperature post-annealing decreases the TDDB characteristics of ultra-thin oxide with polysilicon gate. The charge to breakdown is reduced drastically with increasing the annealing temperature and annealing time. The dielectric breakdown reliability degradation of ultra-thin tunneling oxide by the post-annealing can be explained as the partial oxide thinning and electric field concentration due to the increase of roughness at the polysilicon gate/ultra-thin tunneling oxide interface. This increase of roughness is due to the grain growth of polysilicon gate and viscous flow of oxide, which are enhanced with increasing the annealing temperature and time.