Die Pad Research Articles

On Legalization of Die Bonding Bumps and Pads for 3-D ICs

On Legalization of Die Bonding Bumps and Pads for 3-D ICs

Die Attach Process Robustness through Epoxy Pattern Optimization for DFN Device

As the modern world evolves through innovation and technology, manufacturing companies of semiconductor drive their people to dedicate themselves on continuous improvement and technical advancement. Products they produce becomes smaller and thinner, but applications are limitless and innovative. In manufacturing of quad flat no lead packages, challenges were encountered during the die attach process especially in small die size. Die attach material overflow on pad is one of these, and certain parameters and techniques are explored to have a quality and robust process. Defining appropriate epoxy pattern with respect to the die size is a big factor to make sure no epoxy material will flow outside the die pad perimeter that may cause unit rejection. This paper will discuss the related issues of the said package by performing experiments and applying certain techniques to address the problem.

Theoretical Study on the Adhesion Interaction between Epoxy Resin Including Curing Agent and Plated Gold Surface.

In this study, the adhesive interaction between gold and epoxy resin is theoretically investigated. These materials make up crucial components of a wide range of electronic devices. The objectives of the study are (1) to elucidate the bonding mechanism between epoxy resin and a realistic gold surface, and (2) to obtain a device-design guideline for superior adhesion, thus reducing the bonding breakage that may potentially cause device failure. Die pad surfaces used in chip attachment methods for microelectronics are usually fabricated using an electrolytic plating technique. This technique involves ionic gold solutions like K[Au(CN)2]. The combined theoretical and experimental studies previously carried out by the authors have revealed that the CN- counteranion of the gold cation has a high affinity for gold and is likely to remain on the realistic gold surface generated by plating. However, the cyano group content on the surface of the plated gold is still unknown. Therefore, gold surfaces embedded with cyano groups with various coverages are constructed. The effect of the varying coverage of the cyano groups on the adhesion strength is inspected using first-principles density functional theory calculations. As the number of cyano groups on the surface increases, the direct interaction between the gold surface and the epoxy resin is hindered, but the hydroxy and amino groups in the epoxy resin and hardener form more hydrogen bonds with the cyano groups adsorbed on the surface. It is found that the surface with intermediate cyano coverage (about 33%) yields the highest adhesive strength.

Optimization for Die Attach Film Delamination on Nickel-Palladium-Gold Die Pad

In the Semiconductor Industry, the delamination performance of integrated circuit packaging is being aggressively improved. However, this task is complicated and difficult, as the defective failure is highly dependent on the compatibility of the material characteristics that may affect the entire Integrated Circuit package system under certain stress levels, both mechanical and thermal. This research work aims to study Die Attach process optimization in DAF adhesive for Nickel-Palladium-Gold Die Pad leadframe to achieve maximum reliability performance under IPC / JEDEC Moisture Sensitivity Level 1 (MSL1) at 260°C reflow. Strategic optimization of the Die Attach process is needed to ensure robust reliability. And one of the solutions is to apply the Scrubbing method, which is a machine feature used at a constant temperature to aid in the wetting of adhesives and the removal of voids.

Comparative study of the ideal and actual adhesion interfaces of the die bonding structure using conductive adhesives

ABSTRACT A die bonding interface consisting of a plated gold surface and conductive silver paste was investigated using two approaches: One was a computational method for the ideal interaction, while the other was an experimental technique to get some ideas about the actual bonding. A density functional theory (DFT) calculation was employed to clarify the adhesive interface between the Au (1 1 1) surface and bisphenol-A type epoxy resin which included dicyandiamide as a curing agent. The computational results showed that the cyano group involved in the hardener strongly binds to a gold atom on the ideal surface. This interaction is likely to be assigned to σ-donation and π-back donation. The predicted adhesive strength was 1.15 GPa. To evaluate the real adhesion strength, small-sized single lap-shear joints were fabricated and tensile shear tests were performed. The measured adhesive stress was about 27 MPa. The results of surface analytical methods indicated that the actual die pad surface was not smooth. Furthermore, an altered layer terminated with Au(CN)x was found on the top of the die pad. It was inferred that the mechanism of the actual die bonding interaction would be changed to the formation of hydrogen bonds. This could be a reason why reduced adhesive strength was observed.

Controlling Surface Sensitive Processes in Microelectronics Manufacturing to Improve Wire Bonded Joint Reliability

Abstract Validating surface chemical composition and properties of die pad surfaces is crucial for achieving joint reliability in microelectronic wire bonding operations. Die pad surfaces undergo a number of surface sensitive manufacturing steps prior to bonding that will affect joint performance; contact and environmental contaminants from process aids, shipping, handling, storage and out time are all key players in surface degradation. Microelectronics manufacturers may implement cleaning and/or surface activation operations to remediate surfaces from upstream contaminants, however, understanding and quantifying the effect of such processes requires the ability to manipulate and monitor the top few molecular layers of a material responsible for adhesion—the surface. This presentation will investigate surface chemistries of atmospheric plasma cleaned and non-cleaned die pad surfaces as determined by X-ray photoelectron spectroscopy (XPS) and surface energy measurements via contact angle techniques.

Increasing the Dimensional Accuracy of U-Bend Product of High Strength Steel Sheets by Pressure Pad

To reduce springback in U-shape of high strength steel sheet, the present paper proposes a new process parameter in U-bending technique. This paper aims to present the effect of clearance between die and pressure pad on springback behavior. The process in this work consists of four steps: (1) clamping of a sheet between a punch and a pressure pad, (2) bending with constant clamping force, (3) pushing-up at bottom of the part by using the pressure pad, and (4) final release tool. From the experimental results, decreasing of bending moment by bottom pushing-up resulted in the springback reduction. An appropriate of the clearance between die and pressure pad combined with bottom pushing-up force can be reduced springback. Our results suggested that the Y-U model, an advanced kinematic hardening, is essential for accurate numerical simulation of springback behavior.

Semiconductor-on-Polymer Wafer Level Chip Scale Packaging

Cell phone boards are getting thinner. Labels and tags are getting smarter. Electronics is starting to bend. Consumers think thin is cool. Scaling thickness has and continues to be a key metric in packaging evolution. Chip Scale Packaging (CSP) defines the logical end of package scaling as package area and IC size converge. CSP, as well as the use of bare die, in Direct Chip Attach (DCA) integration pushes the limit of interconnect technology. CSP and implementation of direct interconnect attachment leads to the smallest packages possible. Technology and reliability advances in ultra-thin Semiconductor-on-Polymer (SoP) CSP and direct interconnect assembly is enabling flexible hybrid electronics and sensors today. SoP extends CSP package size reduction to less than 1.0X the die size. Semiconductor-on-Polymer (SoP) CSP results in ultra-thin semiconductor materials that are less than the thickness possible with bare die. SoP was initially introduced to the Flexible Electronics market; the technology has gained interest for conventional low profile, low-mid I/O, DCA type applications. Advanced SoP CSP is an ultra-thin packaging technology that is capable of complete die encapsulation using wafer level processing. Ultra-thin SoP CSP is new package technology. It is applied to fully characterized commercial devices, uses well know semiconductor materials and is generally “qualified by similarity” (QBS). Qualification for flexible applications supplement QBS with test procedures derived from established standards. The initial development of test methods and procedures was done with AFRL support in 2017. Initial reliability for the new flexibility tests will be presented. SoP CSP is undergoing further characterization for conventional applications. This includes testing that is typical of non-hermetic fully encapsulated parts. Flip-chip is the preferred method for assembly of SoP CSP. The ultra-thin package technology feature is fully utilized using Direct Interconnect (DI). Direct interconnect (DI) is defined as the die pad interconnect technology where the pad is connected directly to a board pad of equivalent size and spacing. Direct interconnect is common for low pad count devices such as RFID, NFC and other DCA applications. Direct interconnect is not typically considered for higher pin count devices…until now. This presentation shares the development of SoP CSP DI assembly that has progressed from 24 pin attachment to System-on-Chip assembly of DI pitch at <100um. The presentation also shows the technology roadmap for SoP CSP evolution. A case study of a SoP CSP application will be included with data from a fully assembled ultra-thin electronic system based on a SoP CSP SOC with total thickness less than 30um. The system includes on-board ultra-thin fully flexible sensors. A call to action will be made to embrace ultra-thin electronics. System Designers and IC Engineers will be encouraged to: BUILD! Create the vision for ultra-thin possibilities. Put electronics into places and things never before possible with, prototypes, testing, reporting, and introducing new thin concepts. Reliability Leaders will be encouraged to: TEST! Update test procedures and standards to include physical deformations and then report and challenge the industry to improve. Universities will be called to: CREATE! Generate new physics/models associated with deformations, develop interconnect innovations and advance new materials. In general, the presentation makes the case that hardware matters – Let's build some new technology.

Design of high density SiP for complex computing system in micro SD format

This paper addresses the design process for the miniaturization of a complex computing system within the micro SD format. The complete device is capable of running a Linux OS in a standalone mode. The process is illustrated by a real design example that has been taken through all the steps from architecture through a PCB hardware prototype to a fully integrated miniature SIP solution. The design process starts with a detailed architecture definition describing in detail the individual functions that must be implemented within the design. Once the architecture has been defined a detailed schematic is created, in which care is taken to ensure that all the components will be available in die format or low profile WLCSP so as to fit the low profile of the micro SD card. Prior to starting detail design of the SiP a complete working prototype must be constructed using packaged parts mounted on a PCB. This step ensures that the complete system is functional and any firmware, OS development or software can be tested independently of the SiP. This breadboard also allows for experimentation on passive BoM reduction, a necessary step towards reducing component count prior to SiP integration. A revised schematic for the SiP is created in which the packaged components are replaced by bare die equivalents with all the individual bond pads. Prior to this step negotiations have to be made with all bare die suppliers to confirm availability and obtain detailed information concerning the die pad layout and technology. Appropriate substrate technology choice has to be made. Miniaturization of complex heterogeneous SiPs requires best in world class substrates. In this case extremely high definition 6-layer build up substrates were required with complex plating techniques for wire-bonding compatibility. The detailed design is carried out using standard PCB or SIP layout tools. In the design example a total of 6 dies, 4 packaged parts and 40 small chip SMTs were integrated. A memory stack of 3 dies plus the 6 layer substrate and over-mold was integrated within the maximum height of 0.8mm. This required the use of state of the art Film on Wire with dies thinned to less than 80im. Signal integrity simulations of the substrate are made at this stage for critical parts of the system. The debug process of such complex designs requires constant interaction between breadboard performance and SIP performance to determine root causes for potential failure of the SiP. Since the design has 1000 nets of which only 35 are visible on the SIP, probing is impossible. In the actual design example the miniature micro SD SiP is fully functional and operates as a stand-alone Linux computer.

Influences of the die pad and the ironing process on a side wall thickness and concentricity of the product during multi-stage drawing

Influences of the die pad and the ironing process on a side wall thickness and concentricity of the product during multi-stage drawing

Chip Last Fan Out as an Alternative to Chip First

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages

드로잉 가공에서 다이패드의 독립형과 일체형 구조가 제품 두께에 미치는 영향에 관한 연구

Using a progressive die of the multi-stage drawing product, It was experiments for the Influence of the Products Roundness on the die pad process Safety die model, obstacle countermeasure research safety die design When the die pad is independent structure, Sidewall thickness of the inside 2stage, 3stage, 4stage of the product is thicker, the thickness of the inside 1stage and the bottom is thinner. it was become unstable beacuse the inside 1stage related to the Products Roundness is thinner. When the die pad is Integrated structure, Sidewall thickness of the inside 1stage, 2stage of the product is thicker, and Sidewall 3stage and 4stage was a thin. it was become unstable beacuse the inside 3stage related to the Products Roundness is thinner. Therefore, The appropriate combination of and integrated independent is required for each process.

Low Cost Chip Last Fanout Package using Coreless Substrate

Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices. Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.

An Experimental and Numerical Investigation Into Wafer Probing Parameters Based on Thin Wafer Breaking Strength

Mechanical contact caused using excessive probe force produces an oversized scrubbing mark that may result in damage to the die pad and the silicon chip breaking for thin wafer. Therefore, investigating the relationship between the wafer thickness and the limited breaking stress of the wafer, and applying this relationship as a basis for establishing suitable design rules for a multilayer needle layout are crucial. In this paper, two experimental techniques, three-point-bending test and ball-on-ring, were setup and carried out to measure the force-displacement relation of various wafer thicknesses (100–25 $\mu $ m). The results from the testing then coupled with finite-element analysis to reverse finding the breaking stress/strain as a function of wafer thickness. In addition, experimental setup with a single tungsten needle probe contact with Al pad were employed to investigate the relations between the overdrive, beam length, and scrub mark length. A 3-D computational probing simulation model was developed and verified against the experimental data. The model is then used to examine the effects of the beam length, overdrive distance (OD), and shooting angle on the maximum stress induced within the wafer. Finally, a four-layer probe card needle shape design has been demonstrated as a practical application example; it is shown that for a wafer thickness of 25 $\mu $ m and an OD of 60 $\mu $ m, the allowable shooting angles of a four-layer needle probe card are as follows: 1500 $\mu $ m and 0°–4° (Layer 1); 2100 $\mu $ m and 0°–9° (Layer 2); 3500 $\mu $ m and 0°–15° (Layer 3); and 4000 $\mu $ m and 0°–15° (Layer 4).

Study of Chip–Package Interaction Parameters on Interlayer Dielectric Crack Propagation

To meet the electrical performance requirements, copper traces with ultralow- k (ULK) interlayer dielectric (ILD) materials are used in today's semiconductor devices. The dielectric constant (k) of these materials is often reduced through the introduction of pores or inclusions, and thus, the ULK ILD materials have low fracture strength. During flip-chip assembly, thermally induced stresses occurring due to the differential displacement between the substrate and the die can result either in ILD cracking or in ILD delamination in the vicinity of solder bump. Such reliability problems are a cause for concern in semiconductor devices. In this paper, we study such dielectric cracking through numerical models and experiments and present methods to reduce such dielectric cracking. This work uses a finite-element-based submodeling approach to study ILD cracking in flip-chip assemblies. The developed “global” model accounts for the die, the passivation layer, the die pad, the solder bump, the substrate pad, and various layers in the substrate, including the trace pattern effective directional modulus. The displacement boundary conditions from the global model under flip-chip assembly cooling are then applied to a “local model,” which accounts for the die with its backend-of-line (BEOL) stack details, such as the die pad, the passivation layer, the solder bump, the substrate pad, and layers in the substrate. The local model focuses on the most critical solder bump, based on global stress contours. Next, cohesive cracks are introduced at various locations in the ULK layers above the critical solder bump and are allowed to propagate under flip-chip assembly reflow thermal conditions. It can be seen that the elastic energy available for crack propagation initially increases with crack length, but then starts to decay, indicating that the ILD cracking is often confined in the vicinity of one bump. Furthermore, the results from the models have been compared against experimental failure analysis results of 45-nm (C45) devices. It is also shown that the models can provide geometry and material guidelines to reduce ILD cracking.

A new myth regarding the Great Trek: Reinvention of identity in Die pad na skuilhoek [The path toSkuilhoek] by Hans du Plessis.

This article aims to illustrate how Hans du Plessis, in his novel Die pad na Skuilhoek [The path to Skuilhoek] (a place of shelter), subverts the way in which history had been presented in historical novels in the past by addressing social issues that contemporary readers find relevant. The first part of the article deals with the social codes that shape the identities of the main characters and how these identities are relevant in terms of the social framework within which the novel is received. In the second place the focus will shift towards Du Plessis’s representation of cultural and national identities. The question: ‘Who were the Afrikaners at the time of the Great Trek?’ will be answered with reference to these identities. In conclusion it will be pointed out how Du Plessis avoids dated practices of historical interpretation by choosing ecocrticism as the ideological framework for his novel and is, in this way, constructing a new social myth about the Great Trek.

A New Embedded Package Structure and Technology for the Next Generation of WLP, the Wafer level Fun-Out Package - WFOP (TM)

Presenting a new embedded package structure and technology for the next generation of WLP, the Wafer level Fun-Out Package – WFOPTM. A face-down mounting style, it has a metal stainless or copper plate as a base plate of redistributed interconnection layer. The redistributed layer is fabricated with a semi-additive method of copper plating. The contact between the die pads and distributed layer is the lead type. With this structure we hope to reduce fabrication cost by using large scale panels and precise redistribution interconnect controls, and its design rule does not depend on the die size. Moreover, WFOPTM has several benefits – applicable to 50μm pad pitch, excellent thermal characteristics and noise shield by attaching the metal plate. We obtained fine reliability test results. In this paper, we report its package structure, process flow, package characteristics and reliability test results and discussion.

Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni3P and (Cu,Ni)6Sn5 after thermal aging, while the substrate pad region contains Cu3Sn and (Cu,Ni)6Sn5. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)6Sn5 on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm2/h, 0.1423 μm2/h, and 0.4463 μm2/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.

Power and signal integrity co-design for quad flat non-lead package

The co-design of power and signal integrity issues on a quad flat non-lead (QFN) package is described. A novel decoupling capacitor is achieved by separating the die pad and footprint, coating a solder mask on the footprint and connecting the footprint to the printed circuit board power plane through a via. Large capacitance between power (footprint) and ground (die pad) resulted from the thin mask and large die pad lowering the input impedance of the power delivery network without parasitic effects at low frequency. A power bridge and a ground bridge are introduced to substitute the wire bond to decrease the inductance and hence the impedance magnitude up to 30%, thus enhancing the power integrity at high frequency. A modified design called hybrid power/ground exhibits great signal integrity by providing good reference for signals. The thermal dissipation is also better than the first design through direct contact of the die pad and the footprint ground regions. The overall design demonstrates excellent broadband performance for signal and power integrity.

Electromigration Reliability of Cu Pillar on Substrate Interconnects in High Performance Flip Chip Packages

Manufacturing high performance devices with shrinking form factors require a novel packaging approach. The Cu pillar-on-die interconnect is a widely accepted solution to package high performance flip chip devices due to its fine pitch adaptability, good electrical and thermal characteristics and elongated electromigration lifetime. However, the thick Cu pillar increases the stress on the die pad creating reliability issues due to fracture or de-lamination of low-k and extreme low-k (ELK) inter-layer dielectric layers. μPILR™ technology follows a Cu pillar-on-substrate approach that enables both the decoupling the Cu pillar from the ELK layers and enhanced electro-migration performance. This cost-effective alternative technology employs a subtractive etch process to form Cu pillars on substrates with exceptional intrinsic co-planarity. The 3D nature of the pillars offers advantages of increased vertical wetting for high yield in fine pitch assembly and reduction of crack propagation for good thermal cycle performance. Our preliminary investigations suggest that the electromigration lifetime of μPILR interconnects exceed the published lifetime data on various types of flip chip interconnects. In this work, the electromigration performance of two different interconnects will be investigated within Pb-free fine pitch flip chip packages. Interconnects include etched Cu pillar-on-substrate and conventional thin Cu UBM with solder-on-substrate-pad. The package level test vehicle has a large 18x20x0.75mm die with 10,121 interconnects with a minimum pitch of 150 μm packaged on a 40x40x1.19mm substrate with 10 metal layers in a 3-4-3 build up on a core stack. A comprehensive study of electromigration performance of these interconnects will be presented with the experimental determination of their activation energy and current exponent values. The Black's equation will be solved using mean time to failure data obtained from the experiments. A detailed description of the physical changes during the electro-migration failure process due to inter-diffusion and inter-metallic compound formation will be discussed.