Die Pad Pitch Research Articles

High-density Fan-Out Chip on Substrate using M-Series (TM) and Adaptive Patterning® Technology

As silicon technology nodes advance and wafer costs increase, there is a strong incentive to shrink die size and concurrently, die pad pitch. This increased density typically drives higher cost advanced substrates with finer lines and spaces and potentially more layers. As a result of recent constraints on the substrate supply chain, this creates serious availability and cost concerns. A compelling solution is to use fan-out on substrate technology to increase the effective die pad pitch, allowing the use of simpler, lower layer count substrates. ASE used this single die Fan Out Chip on Substrate (FOCoS) approach in engineering and qualification builds starting in 2017 with a traditional fan-out solution. However, with increasing interconnect density, the conventional approach is limited in its ability to work with small bond pad pitches as the die shift during molding creates challenges for manufacturing. An oversized capture pad is often utilized to accommodate this shift and in one prominent case, an additional Cu layer is required. M-series’ use of Adaptive Patterning eliminates the need for oversized capture pads through a unique design-during-manufacturing process which precisely aligns the package interconnect layers to the actual location of each die after molding. This paper will examine the design and manufacturing of a FOCoS package using 4nm silicon through the cooperation of Deca and ASE. The design fans out the interface of a 12mm x 12mm die with 6,000 IO using a single RDL layer and 5 µm line and space. The die has a core pitch of 150µm with an average periphery pitch of 90µm. The resultant M-series flip-chip bumps have a core pitch of 150µm over 75% of the die area with a secondary pitch of 212µm encompassing the remaining perimeter of the die and the 30% body size growth provided by the fan-out region. The relaxed pitch provided by M-series fan-out opens the possibility to use the most cost-effective, readily available type of laminate substrate.

Advanced Microelectronics Packaging Solutions for Miniaturized Medical Devices

The wide range of applications for medical electronics drives unique requirements that can differ significantly from commercial & military electronics. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. Advanced microelectronics packaging solutions with embedded passives are enabling SWaP reductions. Implementation of these solutions has realized up to 27X reduction in physical size for existing PWB assemblies, with significant reductions in weight. Shorter interconnects can also reduce or eliminate the need for termination resistors for some net topologies. Successful miniaturized products integrate the following design techniques and technologies: component footprint reduction, thin high density interconnects substrate technologies, I/O miniaturization and IC assembly capabilities. This paper presents fabrication and electrical characterization of embedded actives and passives on organic multilayered substrates. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on embedded chips, resistors, and capacitors. Embedded passive technology further enhances miniaturization by enabling components to be moved from the surface of the substrate to its internal layers. The use of thin film resistor material allows creating individual miniaturized buried resistors. These resistors provide additional length and width reduction with negligible increases to the overall substrate and module (SiP) height. Resistor values can vary from 5 ohm to 50 Kohm with tolerances from 5 to 20% and areas as small as 0.2 mm2. The embedded resistors can be laser trimmed to a tolerance of <5% for applications that require tighter tolerance. The electrical properties of embedded capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide frequency and temperature range. A few test vehicles were assembled to do system level analysis. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch. In addition, new technologies for embedding a variety of active chips are being developed. A variety of active chips, including a chip having dimensions of one millimeter square, have been embedded and electrically connected to develop high performance packages.

Miniaturization of Electronic Substrates for Medical Device Applications

The medical industry is clearly and urgently in need of development of advanced packaging that can meet the growing demand for miniaturization, high-speed performance, and flexibility for handheld, portable, in vivo, and implantable devices. To accomplish this, new packaging structures need to be able to integrate more dies with greater function, higher I/O counts, smaller die pad pitches, and high reliability, while being pushed into smaller and smaller footprints. As a result, the microelectronics industry is moving toward alternative, innovative approaches as solutions for squeezing more function into smaller packages. In the present report, key enablers for achieving reduction in size, weight, and power (SWaP) in electronic packaging for a variety of medical applications are discussed. These enablers include materials selection, embedded passives and active devices, System-in-Package (SiP) designs, and flex circuits. Manufacturing methods and materials for producing advanced organic substrates and flex along with ultra fine pitch assemblies are discussed. A case study detailing the fabrication of a flexible substrate for use in an intravascular ultrasound (IVUS) catheter demonstrates how the challenges of miniaturization are met. These challenges include use of ultra-thin polymer films, extreme fine-feature circuitization, and assembly processes to accommodate die having reduced die pad pitch.

Nano‐ and micro‐filled conducting adhesives for z‐axis interconnections: new direction for high‐speed, high‐density, organic microelectronics packaging

PurposeThe purpose of this paper is to discuss the use of epoxy‐based conducting adhesives in z‐axis interconnections.Design/methodology/approachA variety of conductive adhesives with particle sizes ranging from 80 nm to 15 μm were laminated into printed wiring board substrates. SEM and optical microscopy were used to investigate the micro‐structures, conducting mechanism and path. The mechanical strength of the various adhesives was characterized by 90° peel test and measurement of tensile strength. Reliability of the adhesives was ascertained by IR‐reflow, thermal cycling, pressure cooker test (PCT), and solder shock. Change in tensile strength of adhesives was within 10 percent after 1,000 cycles of deep thermal cycling (DTC) between −55 and 125°C.FindingsThe volume resistivity of copper, silver and low‐melting point (LMP) alloy based paste were 5 × 10−4, 5 × 10−5 and 2 × 10−5 Ω cm, respectively. Volume resistivity decreased with increasing curing temperature. Adhesives exhibited peel strength with Gould's JTC‐treated Cu as high as 2.75 lbs/in. for silver, and as low as 1.00 lb/in. for LMP alloy. Similarly, tensile strength for silver, copper and LMP alloy were 3,370, 2,056 and 600 ψ, respectively. There was no delamination for silver, copper and LMP alloy samples after 3X IR‐reflow, PCT, and solder shock. Among all, silver‐based adhesives showed the lowest volume resistivity and highest mechanical strength. It was found that with increasing curing temperature, the volume resistivity of the silver‐filled paste decreased due to sintering of metal particles.Research limitations/applicationsAs a case study, an example of silver‐filled conductive adhesives as a z‐axis interconnect construction for a flip‐chip plastic ball grid array package with a 150 μm die pad pitch is given.Originality/valueA high‐performance Z‐interconnect package can be provided which meets or exceeds JEDEC level requirements if specific materials, design, and manufacturing process requirements are met, resulting in an excellent package that can be used in single and multi‐chip applications. The processes and materials used to achieve smaller feature dimensions, satisfy stringent registration requirements, and achieve robust electrical interconnections are discussed.