Die Bond Pad Research Articles

Environmentally Hardening IC Die Previously Assembled in Plastic Packages through Die Removal, Bond Pad Replating and Reassembly into Hermetic Packages

ABSTRACT Many integrated circuits (ICs) will operate well above their maximum rated temperature of +70°C or +125°C, but are often not packaged appropriately to reliably endure temperatures above +150C. Specifically, the original gold or copper bonds on the aluminum die bond pads are prone to Kirkendall or Horsting voiding, particularly at temperatures greater than +150°C. Also the mold compounds used in plastic packaging for IC assembly can degrade at these elevated temperatures. In some cases, commercial demand for higher temperature reliability can justify a separate offering of ICs assembled in hermetic, ceramic packages from the original component manufacturer (OCM). However, in most cases, the market demand is deemed insufficient. Global Circuit Innovations (GCI) has developed a high-yielding process, which can remove a semiconductor die (i.e., computer chip) from a plastic package, remove the original bond wires and/or ball bonds, plate the aluminum die bond pads with Electroless Nickel, Electroless Palladium, and Immersion Gold (ENEPIG), and then reassemble the now improved semiconductor die into a hermetic, ceramic package. Device Extraction, ENEPIG die bond pad plating and Repackaging (DEER) provides an improved die bond pad surface such that works well with either gold or aluminum bond wires in applications up to +250°C without mechanical or electrical connectivity degradation. GCI routinely exposes sample devices to +250°C bakes with 100% post bake yields so as to continuously ensure that any device processed with the DEER technology will reliably perform in high-temperature environments. Although the oil and gas industry has already expressed significant interest in the DEER process, with excellent lifetest and production application results demonstrating dramatically increased component lifetimes at elevated temperatures, this technology can also be leveraged for any application exposing ICs to harsh environments. Not only is the high-temperature reliability dramatically increased, but also the new hermetic, ceramic package protects the IC from a variety of elements and environments (i.e., corrosives and moisture).

Journey to Success for New Analog Technologies for Texas Instruments

Abstract TI's commitment to meeting customer requirements has resulted in the development of package technologies and process to improve performance and higher power at lower cost for wire-bonded packages and automotive products are requiring more stringent reliability requirements. Some of the strategies we have adopted include using thinner metal and low-K ILD for lower parasitics and higher performance, thick copper routings for higher power and larger wafer diameters and smaller scribe streets for lower cost and using Copper (Cu) wire. Cu wire is a key enabler due to higher electrical conductivity and lower cost than gold), but also poses integration challenges due to hardness, CTE mismatch and corrosion susceptibility. The hardness of the copper wire imposes significant challenges for wire-bonding on pads w thin metal and low-k ILD. This required co-design of die bond pad structure for enhanced reliability as well as Cu wire process development requires comprehensive approach encompassing multiple areas including ball and stitch parameters, capillary design, bonding processes like segmented bonding and validation of process margins using ‘hammer’ test. Copper wire also requires metrology and test/detection tools like Nomarski, stitch pull test in addition to the traditional wire pull at mid span and neck, rapid-bake test, measuring intermetallics & Al remaining under ball, and Al-splash. The susceptibility of Cu wire to corrosion required us to introduce new materials like PCC and Au-flash PCC, tight environmental controls in the form of forming gas, monitoring of Ph and ion-trappers in BOM, wire oxidation check at outgoing/incoming inspection as SERA (Sequential Electrochemical Reduction Analysis), and paying close attention to handling and non-process gases. More stringent qualification requirements like AEC-006 is driving additional changes to lead frame design and finish, selection of EMC and Die attach, to reduce delamination and epoxy bleed-out. The demands for lower cost is driving us to use larger sized wafers (like 300mm) and narrower scribe width, while packing more functionality into smaller dies thereby driving higher metal densities. Additional requirements for thinner and 3D packages requiring post backgrind thickness as low as 50–75um imposing challenges in terms of warpage and saw. The demand for higher power applications is requiring us to use thick copper routings. We have developed test structures and redesigned layout of the scribe street and scribe seal and pursuing new saw methods. We have also learned many lessons in terms of handling and corrosion risks and implemented safeguards in terms of process and material selection.

Improved Bond reliability through the use of Auxiliary Wires (Security Bumps and Stand-Off Stitch)

Whether the need is due to poorly bondable materials, non-flat bonding surfaces, odd packaging situations, or just the need for high reliability; the integrity of a wire bond interconnect can usually be greatly improved through the proper use of Auxiliary Wires. Auxiliary Wires are defined as Security Wires, Security Bumps, or Stand-Off Stitch (aka Stitch on Bump). The old stand-by Security Wire has been an asset for several decades, however, this is being replaced by Security Bumps which require a smaller second bond termination area. Further, Stand-Off Stitch (SOS) has many more applications and also has many side benefits that could be incorporated into a circuit design for better wire strength properties, fewer interconnects (die to die bonding), and lower loops. Stand-Off Stitch bonding involves the placement of a ball bump at one end of the wire interconnect, then placing a wire with another ball at the other end of the interconnect and stitching off the wire on the previous placed ball bump. This results in a near homogeneous stitch bond interconnect to the bump with an inherent improvement in stitch bond pull strength. Another use for SOS is Reverse Bonding (Stitch bond on bump on die bond pad) often resulting in a lower loop profile than standard forward wire loop and the loop is stronger because the wire hasn't been work annealed above the ball (in the Heat Affected Zone). A major impediment to the implementation of SOS is the retraining of visual inspectors and the approval of quality departments.

Effect of wire diameter on the thermosonic bond reliability

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6 mil and 0.8 mil diameter wires) shows formation of voids apart from intermetallic compound growth. While, with 1-mil and 2-mil diameter gold wire bonds the void growth is less significant and reveal fine voids. Studies also showed void formation is absent in the case of thicker 3 mil wire bonds. Similar tests on copper ball bonds shows good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as any voids on the microscopic scale and thus exhibits to be a better design alternative for elevated temperature conditions.

Effect of wire size on the formation of intermetallics and Kirkendall voids on thermal aging of thermosonic wire bonds

Thermosonic bonding process is a viable method to make reliable interconnections between die bond pads and leads using thin gold and copper wires. This paper investigates interface morphology and metallurgical behavior of the bond formed between wire and bond pad metallization for different design and process conditions such as varying wire size and thermal aging periods. Under thermal aging, the fine pitch gold wire ball bonds (0.6- and 0.8-mil-diameter wires) show formation of Kirkendall voids apart from intermetallic compound growth. With 1- and 2-mil-diameter gold wire bonds, the void growth is less significant and reveals fine voids. Studies also showed that void formation is absent in the case of thicker 3-mil wire bonds. Similar tests on copper ball bonds show good diffusional bonding without any intermetallic phase formation (or with considerable slow growth) as well as no voids on the microscopic scale and thus promises to be a better design alternative for elevated temperature conditions.

Rapid Prototype Fabrication of Custom Chip Scale Packages

ABSTRACTMany new electronic systems require very high-density packaging to meet system volume and weight constraints. The Chip Scale Package (CSP) is often used to meet this need. However, the limited commercial availability of die in CSP form frequently drives system designers to pursue custom CSP fabrication. Long lead times and manufacturers' reluctance to run small batches typically limit the use of custom CSPs to high volume applications. This paper presents an approach for the rapid prototype of Low Temperature Co-fired Ceramic (LTCC) CSPs.Integral to the approach is the concept of using a small family of generic substrate designs to build a large variety of CSPs. The generic substrates may be fabricated and kept on hand until a CSP application need arises. When it does, a 12-to-16-week industry-typical lead time does not apply; the CSP may be fabricated rapidly, on site. Fabrication consists of simply singulating the substrate, populating the solder ball pads, mounting and wire bonding the die, encapsulating the substrate surface, and laser marking the assembly. The lead time may be slashed from several months to just a few days.The family of substrate designs will be described. The substrates, with gold-based interconnects, have standard JEDEC Ball Grid Array (BGA) footprints of either 0.8 mm or 1.0 mm pitch. Substrates have a top surface metallization scheme of either a large central die bond pad surrounded by a number of peripheral bond sites for wire bonds, or a blanket metallization layer that may be patterned, via photolithography, to accommodate a specific application at the time of need. The die pad design is used for CSPs with a single die, while the blanket metallization design is patterned for hybrid or multi-die applications. The design approach, custom photopatterning and gold etch, and assembly processes are presented.

UNDER BUMP METALLISATION OF FINE PITCH FLIP-CHIP USING ELECTROLESS NICKEL DEPOSITION

For solder based flip-chip assembly, under-bump metallisation (UBM) layer deposition on the Al die bondpads is the first step in the wafer bumping process. The UBM is necessary, as the fragile Al pad has a tough oxide layer that cannot be soldered without the use of strong flux and a barrier layer is required to prevent dissolution of the bondpad into the solder during reflow. The UBM requirements are therefore to provide a solder wettable surface and to protect the underlying Al bondpad during and after assembly. In addition, the UBM deposition process itself must remove any oxide layers on the bondpads to ensure a low resistance interface between pad and UBM. This paper reports a study of the electroless nickel deposition process for the UBM of wafers that are subsequently to be bumped using solder paste printing. This work has extended the process from previous trials on 225 /spl mu/m pitch devices to wafers including die with sub-100 /spl mu/m pitch bondpads. The effect of the various pre-treatment etch processes and zincate activation on the quality of the final electroless Ni bump has been investigated. SEM examination of samples at each stage of the bumping process has been used to aid detailed understanding of the activation mechanisms and to determine their effects on the electroless Ni bump morphology. In addition, bump shear testing has been used to determine the best pre-treatment regime to ensure good adhesion of the electroless Ni to the bondpad. Finally, bumped die electrical resistance measurements have been used to confirm that the pre-treatment procedures are producing a low resistance interface between the Al and electroless Ni.