Integrated Circuit Packaging Research Articles

Research and development of public service platform for integrated circuit test

Integrated circuit (IC) test is a key technical part of IC chain, which works through the entire life cycle of IC design, manufacturing, packaging, and application. Based on the increasing requirements of IC test, this paper analyzes the breakthrough point to promote the development of IC test and puts forward an accurate and feasible programme of public test platform construction so as to achieve long-term sustainable development of IC industry.

Epoxy Molding Compound Filler Clogging Simulation During Integrated Circuit Encapsulation Process

As IC components become denser and smaller in a package, more problems emerge. In the mold filling process, because epoxy molding compound (EMC) contains approximately 80 wt.&#x0025; silica fillers, the fillers may clog at the gate of gap if the gap height between the component and the substrate is too small. This clogging will cause a popcorn effect due to the high resin content in the gap. In order to determine the EMC filling process in the mold cavity and the relation between the gap height and the filler size, we simulate the EMC filling process and the EMC filler concentration distribution in the mold cavity using mold flow analysis software and then use computational fluid dynamics-discrete element method (CFD-DEM) coupling method to simulate the EMC filler motion to determine the relationship between gap height and filler size and the factors that affect filler clogging. Based on the mold flow analysis results, the filler concentration was higher at the gate of gap than in other regions, and the filler concentration at the gate of gap for the 30-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gap-height model was higher than that for the 50-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> gap-height model. Based on the DEM-CFD coupling results, particles with a single diameter larger than one-half of the gap height caused particle clogging the gate of gap, and particles with a mean particle size larger than one-third of the gap height caused particle clogging the gate of gap.

Nano-joining Mechanisms and Joint Reliability of Die Attachment Using Bimodal-sized Cu Nanoparticle Paste Capable of Low-temperature Pressureless Sintering

Nano-joining Mechanisms and Joint Reliability of Die Attachment Using Bimodal-sized Cu Nanoparticle Paste Capable of Low-temperature Pressureless Sintering

Microstructure of Ag Nano Paste Joint and Its Influence on Reliability

In this paper, the microstructure of Ag nano paste joint was investigated in pressure-less sintering conditions, and the influence of the microstructure on the joint’s reliability was studied. Firstly, silver nanoparticles (Ag NPs) were synthesized using the redox reaction method. To tightly stack the Ag NPs in nano paste, Ag NPs with sizes of 30~50 nm and submicron-sized Ag particles were mixed. It was found that increasing the sintering temperature or sintering time can reduce the porosity of the bonding layer and the interfacial crack simultaneously, resulting in higher shear strength. When sintering at a temperature of 250 °C, a complete bonding interface was formed, with a 0.68 μm interdiffusion layer. At a higher temperature (300 °C), the bonding interface reached 1.5 μm, providing 35.9 ± 1.7 MPa of shear strength. The reliability of the die attachment was analyzed under thermal shocking from −65 °C to 150 °C for 50 cycles. As the crack could quickly grow through the interfacial defects, the separation ratio was 85% and 67% when sintered at 150 °C and 200 °C, respectively. Because of the reliable bonding interface between the die and the substrate, the Ag nano paste joint formed a slight crack on the edge of the die when sintering at 250 °C. When the joint was sintered at 300 °C, the small voids became large voids, which featured lower resistance to crack growth. Thus, instead of further improved reliability, the separation ratio increased to 37%.

Relaxed Tolerance Low-Loss Adiabatic Si3N4 to Polymer Waveguide Coupler for Dense Interconnects

Despite significant advances in silicon photonics, optical packaging and interconnection of photonic integrated circuits constitutes a large portion of the associated manufacturing costs. Optical fibers are the dominant approach to optical interconnection. However, techniques that rely on fibers lack scalability, have low efficiency and show poor misalignment tolerance. Proposed alternative solutions using polymer waveguides have shown improved coupling efficiency, misalignment tolerance and scalability. Here we present the design, simulation and the experimental confirmation of an adiabatic silicon nitride taper to polymer waveguide coupler with only 0.52 dB of TE coupling loss at 1550-nm wavelength, excluding material loss. The coupler demonstrates $\pm 4~\mu \text{m}$ of lateral misalignment tolerance with a 1-dB penalty which, to the best of our knowledge, is the highest reported tolerance for silicon nitride to polymer waveguide coupling.

Pressureless Sintered-Silver Die-Attach at 180 °C for Power Electronics Packaging

Die attachment by pressureless silver sintering at <; 200 °C is significant for power electronic packaging because it can relieve residual thermo-mechanical stress and avoid chip damage. In this letter, we developed a trimodal-silver paste capable of pressureless sintering at as low as 180 °C due to the usage of trimodal-system and 170 °C removable organics agents. The bondline could be densified by neck-formation as expected. Thanks to the high packing density of the trimodal system, a high bonding strength of 35 MPa was achieved. Moreover, IGBT modules were demonstrated using the 180 °C sinterable sintered-Ag die attachment. The output I-V characteristics and the thermal resistance of the IGBT modules were discussed.

Investigations of an Influence of the Assembling Method of the Die to the Case on Thermal Parameters of IGBTs

This article presents the results of investigations illustrating the influence of the method of assembling the die of the insulated gate bipolar transistor (IGBT) to the base of the TO-220 lead frame on its thermal parameters. The properties of the tested semiconductor die and the methods of assembling it in the case are presented. The measurement method used here, belonging to the indirect electrical methods, is carefully described. The obtained measurement results are shown and discussed to indicate which of the assembly methods of the die attachment to the case ensures the most effective heat dissipation. The results obtained for the tested devices point to soldering, and they are comparable with the results of measurements obtained for a commercial IGBT mounted in the same case.

Reliability of Ag Sinter-Joining Die Attach Under Harsh Thermal Cycling and Power Cycling Tests

Reliability of Ag Sinter-Joining Die Attach Under Harsh Thermal Cycling and Power Cycling Tests

An inductorless piezoelectric energy harvesting interface circuit using gyrator induced voltage flip technique

PurposeThe purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications.Design/methodology/approachThis paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load.FindingsThe experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting.Originality/valueTo the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.

Micro Solder Joint Reliability and Warpage Investigations of Extremely Thin Double-Layered Stacked-Chip Packaging

Abstract To overcome the limited operational speed for nanoscaled transistors, scaling electronic devices to small and thin packaging and high-density arrangements have become the technological mainstream in designing versatile packaging architectures. Among these, a promising candidate is a three-dimensional integrated circuit (3D-IC) package due to its excellent capability of heterogeneous integration. However, sequential reliability is a troublesome concern given the complex packaging structure, especially for the assembly of microsolder joints. To address this issue, we propose a double-layered, thin stacked chip package under the application of temperature cycling load. The packaging warpage and creep impact of SnAg microsolder joints on their fatigue lifespan are examined separately. Nonlinear material/geometry finite element analysis (FEA) is used on important designed factors, including the elastic modulus of underfill, chip thickness, and the radius and pitch of through silicon via (TSV). The simulated results indicate that the best fatigue lifetime of SnAg microsolder joint can be achieved at 10 μm of each chip thickness, 230 μm and 5 μm for TSV pitch and radius within the examined designed extent. Moreover, a hard underfill material requires consideration when the mounted chips thicken. Consequently, reliability significantly improves by dispersing thermomechanical stress/strain of the SnAg microjoints to neighboring underfill and related packaging components, especially for large TSV array spacing.

Influence of Textured Nickel/Palladium/Gold-Silver (Ni/Pd/Au-Ag) Layer on Pre-plated Leadframe for Automotive Applications

High quality and reliability of integrated circuit packaging is required for automotive applications due to the safety concerns. Therefore, elimination and controlling the package defects which can lead to reliability failure is essential. One of the defects that leads to reliability issue is delamination. This study presents the influence of textured leadframe surfaces on the surface wettability and delamination occurrence in automotive package unit. Standard bare Cu leadframe was used as comparison. The leadframe surface was textured with Ni/Pd/Au-Ag using electroplating technique. The surface morphologies of both bare and textured leadframe were characterized using field-emission scanning electron microscope and optical profiler. The energy dispersive spectroscopy was used to quantify the elemental composition of the samples. All samples went through the wettability test under two conditions, which were room temperature and 175°C. The reliability test of complete package was subjected to moisture sensitivity preconditioning level 1 according to IPC/JEDEC STD 020 and the baking process was performed at 125°C for 24hrs followed by soaking process under the condition of 85°C and 85 of relative humidity. Scanning acoustic tomography according to IPC/JEDEC STD 035 was performed after three cycles of infrared reflow at 260°C. Higher surface roughness was observed for pre-plated leadframe (PPF) compared with bare leadframe. The lowest value of average contact angle (∼55°) was observed for PPF at 175°C indicated better wettability feature. Furthermore, no delamination occurrence was observed for PPF sample compared with bare copper leadframe. The obtained result reveals that leadframe with textured surface of Ni/Pd/Au-Ag improved interfacial surface adhesion which eliminated the delamination defect and thus improved the package robustness and reliability.

Thermally-Induced Deformations and Warpages of Flip-Chip and 2.5D IC Packages Measured by Strain Gauges.

The thermal warpage problems in integrated circuit (IC) packaging exist in both flip-chip and two-and-a-half dimensional integrated circuits (2.5D IC) packages during manufacturing processes and thermal cycling service. This study proposes a simple and easy-to-use strain gauge measurement associated with a beam model theory to determine the thermally induced deformations and warpages of both packages. First, validation and limitations of the beam model theory are presented. Then, the thermally induced out-of-plane deformations for both packages are well described by the finite element method (FEM) simulation with a good consistency to full-field shadow moiré experimental results. The strain gauge measurements were implemented experimentally, and the thermal strain results were found to be well consistent with validated FEM ones. As a result, out-of-plane thermal deformations and warpages of the packages, calculated from the beam model theory with extracted curvature data from the strain gauge, were in reasonably good agreement with those from FEM analysis and shadow moiré measurements. Therefore, the strain gauge method of featuring point strain measurement combined with the beam model theory proved feasible in determining the thermal deformations and warpages of both IC packages.

Laser DAF Cut: A Breakthrough Approach of Die Attach Film Singulation for Thin Wafers

Today, semiconductor world is becoming more inclined to thinner Integrated Circuit (IC) packages. IC packages will require thinning of the internal configuration of the package, which involves the die or the wafer and the adhesive material, which is the Die Attach Film (DAF). Aligned to this, as wafers goes thinner it becomes more of a challenge in process development especially during its preparatory stages, such as wafer back grinding and sawing processes. As the die becomes smaller and thinner wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality.&#x0D; New technologies were introduced so as to adopt to this development trend, one of this is the Dicing Before Grinding (DBG). Compared to the normal wafer preparation process that is wafer back grinding before wafer sawing, DBG flow is wafer sawing first prior wafer back grinding processes. The application of DBG technology eliminates the mechanical draw backs of the conventional wafer sawing process. In addition, with the use of DAF for thinner packages, DBG was developed together with the Die Attach Film (DAF) cutting solution, which is Laser DAF Cutting. DAF are separated using Laser as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw.&#x0D; The paper discuss the Laser DAF cut development that covers the Design of Experiments (DoE) to understand the different characteristics of Laser DAF solution and be validated through actual simulation and wafer processing. The paper will also cover the interaction of different DAF thicknesses and Laser DAF parameters in order to define the critical characteristics so as to understand the behavior of different laser DAF parameters in achieving optimal DAF cutting process responses.

Transient Analysis of ESD Protection Circuits for High-Speed ICs

Electrostatic discharge (ESD) failures in high-speed integrated circuits (ICs) cause critical reliability problems in electronic devices. Transient voltage suppressor (TVS) diodes are installed on high-speed I/O traces to improve system-level ESD protection. To protect the circuit, the majority of ESD current must flow into the external TVS diode rather than into the IC, but due to turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior, the TVS diode may not snap back when needed and the IC's internal protection may take most of the current. These race conditions between the internal and external ESD protection circuits were investigated for a universal serial bus(USB) interface board. The transient turn- <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> behavior of the on-chip and off-chip protection circuitry was characterized by measurements and by system efficient ESD design (SEED) simulations. The effect of transmission line pulses (TLP pulses) and power supply voltages of different sizes on the response of the protection circuitry were monitored and compared with SEED simulations. SEED models showed good agreement with measurements and were used to study the impact of passive components added to a high-speed trace or within the IC package on the ESD protection response. Results show the importance of properly accounting for the parasitic resistance and inductance between the on-chip diode and off-chip TVS diode, as well as the length of the transmission line when choosing the external TVS device. Results also show that testing must be performed using mid-level events to account for possible problems due to race conditions.

Reliability evaluation of ultra thin 3D-IC package under the coupling load effects of the manufacturing process and temperature cycling test

In the development of semiconductor packaging technology from planar to three-dimensional vertical integration, chip interconnection density has increased, and the distance of signal transmission has dropped to improve overall device performance. In this research, an architecture composed of through‑silicon via (TSV) and solder microbump (μbump) is utilized to assemble an ultra thin-type chip into a three-dimensional integrated circuit (3D-IC) package. To explore the influence of residual thermomechanical residual stress induced during the manufacture of the 3D-IC package on the subsequent reliability of the thermal cycling test (TCT), this study establishes a nonlinear simulation methodology for investigating the coupling effect of the manufacturing process and the TCT. The plastic and creep behaviors of the solder μbump are considered in the finite element modeling. The concerned geometric dimensions and underfill materials are also parametrically analyzed. Furthermore, the inelastic strain accumulated in the crucial SnAg solder μbump is examined. Results indicate that the residual strain in the manufacturing process causes an obvious packaging warpage and converges at the subsequent TCT stage. The creep of the solder μbump increases up to 50% in thermal cycling, thereby highlighting the importance of considering the creep model. Moreover, the parameterization of chip thickness can minimize the inelastic strain increment of the solder μbump, and the low Young's modulus of the underfill materials exerts a significant effect on the warpage of the packaging module and the stress compliance of the μbumps.

Damage detection technique using ultrasonic guided waves and outlier detection: Application to interface delamination diagnosis of integrated circuit package

This paper presents the development of a robust data-driven damage diagnosis technique to accurately detect sealant delamination in an integrated circuit (IC) package. A sealant is used to bond the integrated heat spreader (IHS) to the substrate of IC packages for effective thermal dissipation. Delamination of the sealant causes significant reduction in heat management capability of the package, which leads to degradation of processor performance and component reliability. In this work, non-destructive evaluation (NDE) using ultrasonic guided wave (UGW) is performed to interrogate the integrity of the IC package. The advantage of using UGW is its large area inspection capability and small defect detection sensitivity. Ultrasonic tests using a pitch-catch active sensing method with removable piezoelectric (PZT) tranducers are performed with a wide range of excitation frequencies to classify various delamination scenarios in the IC package. Data preprocessing and Hilbert transform-based feature extraction method are also performed on the collected UGWs to extract dominant UGW features. Pattern analysis using a density-based spatial clustering of applications with noise (DBSCAN) algorithm is conducted on the UGW feature space to classify the damage indicators. These damage indicators (outliers) are then used to identify the IC packages with sealant delamination. The proposed technique is validated by comparing it to dye-and-pry tests, delamination metrics, and detection method using a multivariate Gaussian model. The results demonstrate that the proposed diagnosis technique has the potential to be a part of the industrial quality assurance process for IC packages for its capability to detect manufacturing defects with high accuracy.

Impact of alkaline earth oxides on dielectric properties of photoetchable glasses as interposers for integrated circuits packaging

Photoetchable glasses (PEGs) are widely used in integrated circuits as interposers. However, the high dielectric losses intrinsic of PEGs limit their applications in three-dimensional system packaging. Doping with alkaline earth oxides changes the network structure of the PEG, restricting migration of cations, and reducing structural and conduction losses in the glass. After UV exposure and annealing, the dielectric constant and dielectric loss decreases to 4.1 and 0.0025, respectively. Doping with alkaline earth oxides does not significantly decrease the glass transition temperature or viscous flow properties and thus the preferred use of PEGs as interposers. The breakdown filed strength of PEGs can reach 112 kV/cm, which increases their utility and range of applications. Analyses by X-ray diffraction and Raman spectroscopy reveal that alkaline earth oxides form polyhedra resulting in more complex glass networks. A small number of alkaline earth oxides can reduce their dielectric loss. Overall, the introduction of alkaline earth oxides improves their dielectric properties and breakdown filed strength, making PEGs more suitable as VLSI interposers.

Dihydromyricetin modification of boron nitride micro-sheets and construction of multilayer thermal conduction pathways in glass fiber reinforced epoxy composites

In this paper, a novel non-covalent treatment method for the micron-sheets of inert hexagonal boron nitride (h-BN) was proposed by using natural flavonoid dihydromyricetin as modifier. The modified micro-sheets were further applied to fabricate thermally conductive glass fiber cloth reinforced epoxy (GFREP) composites. Specifically, the mixture of high concentration h-BN, acrylate copolymer and epoxy monomers were firstly coated on glass fiber cloth (GFC) to construct in-plane thermally conductive layer, and reduce the interfacial heat resistance between GFC and epoxy matrix. Afterwards, lower concentration h-BN was compounded with epoxy matrix, which provided through-plane thermal conductive paths and avoided excessive deterioration of mechanical properties. The produced GFREP composite exhibited high tensile strength retention (78.1%), excellent in-plane (2.36 W m−1 K−1) and through-plane (0.76 W m−1 K−1) thermal conductivity at 29.6 wt% h-BN content. This study offered an efficient way to develop high-performance GFREP composites with prominent thermal conductivity for integrated circuit packaging applications.

Evaluation of the Quality of BGA Solder Balls in FCBGA Packages Subjected to Thermal Cycling Reliability Test Using Laser Ultrasonic Inspection Technique

In modern integrated circuit (IC) packaging, it is difficult to perceive and evaluate the quality of the solder ball interconnections due to their complex hidden physical configuration and miniaturization. Laser ultrasonic inspection (LUI) technique is a novel, nondestructive, and noncontact method that has achieved great success in evaluating the quality of interconnections in chip-scale and ball-grid array (BGA) packages. In this article, an enhanced dual-fiber array LUI system is used to evaluate the quality of BGA solder balls in advanced industrial flip-chip BGA packages subjected to thermal cycling reliability tests. LUI results are validated with electrical testing, scanning electron microscope (SEM), and dye-and-pry results. LUI results are well correlated with the intermetallic compound cracks in BGA solder balls observed using SEM, and dye-and-pry. This study demonstrates the feasibility of using the LUI system for one of the modern IC packages and the potential to use the LUI system for future advanced IC packages such as 3-D packaging.

Establishing Robust Control for Epoxy Open Time

The Open time is called the time it takes for this chemical transition from liquid to solid. The epoxy moves into a gel state from the liquid state as it recovers, until it enters a solid-state. This article will address the development of a new, regulatory-compliant in die attach epoxy that establishes robust Epoxy Open Time control to improve the performance of product reliability with the following quality output response characteristic in Die Attach was consider; Epoxy Coverage, epoxy voids, Bond Line Thickness (BLT), and Die Shear Test (DST) strength response.