Dickson Charge Pump Research Articles

Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced charging and discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90-nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0 us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be −100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (−27 °C, 0 °C, 27 °C, 84 °C) and at various corners (NN, FS, SF, SS, FF) making it reliable in adverse circumstances.

A frequency boosting technique for cold-start charge pump units

A novel frequency boosting design technique for charge pump architectures is proposed, enabling high speed performance with no additional circuitry or design complexity. The charge pump's oscillator exploits the boosted output voltage of the topology, to provide higher switching frequency to the pumping capacitors. A Dickson charge pump using native NMOS devices is designed and fabricated in XFAB 0.18-μm process, as a product vehicle. The proposed solution is theoretically analyzed and compared to the standard approach. Mathematical analysis, together with simulation results and hardware measurements confirm the validity of the proposed technique, as well as its advantages versus the standard design methodology.

Very-Low-Voltage Charge Pump Topologies for IoT Applications

This paper presents and discusses two Dickson charge pumps that are capable of working with a supply voltage lower than the MOS threshold voltage and are particularly suited for energy-constrained applications. Specifically, the paper includes a theoretical analysis of a previous topology introduced by the authors, and then it discusses a novel topology which solves drawbacks of the previous one. The paper also includes a comparison with other conventional topologies, namely the latched and the four-phase charge pumps, that shows the inherent advantage of the proposed solutions also in the range of input values higher than the MOS threshold voltage. 2-, 4-, and 6-stage versions of the conventional and proposed CPs have been fabricated in a 65-nm standard CMOS technology having a MOS threshold voltage equal to about 440 mV. Experimental results confirm the analytical predictions since the proposed topologies work at input voltage equal to 300 mV with a current load equal to 20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> A and also confirm the advantages of the two proposed solutions in terms of settling time, output current drivability and output power density for voltages slightly higher (450 mV) than the MOS threshold voltage.

An Adaptive Fully Integrated Dual-Output Energy Harvesting System With MPPT and Storage Capability

This paper presents a fully-integrated adaptive dual-output power management system with storage capability for thermoelectric energy harvesting applications. The first output delivers the load power and is regulated at 1.6 V. This output is provided by the primary path of the system that is implemented using a 5-stage reconfigurable Dickson charge pump. In case of the presence of more available power than the load demand, a secondary path is enabled to store the excess amount of energy on a supercapacitor. This provides the second output of the system that is capable of charging up to about twice the voltage of the first output. Besides storing the excess energy, a new technique using the secondary path is proposed for regulating the first output and achieving the maximum power point tracking of the input source. The proposed system is automatically reconfigured to maximize the end-to-end efficiency with the aid of a finite state machine. The system is implemented in 180nm CMOS technology. It utilizes a total on-chip flying capacitance of 2.1 nF, and operates across an input voltage range from 0.35 V to 1 V. Measurement results show that the system achieves an end-to-end efficiency of 72% at a total output power of 1.24 mW.

2.4 GHz 대역 무선전력전송 고효율 수신부 IC 설계

A high-efficiency wireless power transfer-receiver IC that can operate at 2.4 GHz has been proposed. The IC consists of a matching network, rectifier, and DC-DC converter. The rectifier based on the Dickson charge pump topology is designed to have high efficiency by optimizing the number of stages and matching networks. In the proposed IC, a high-efficiency CMOS step-up/step-down DC-DC converter that can operate over a wide input range is involved. The converter provides quadruple conversion ratios of 1/3, 1/2, 2/3, and 2/1, which are determined by the mode selector by sensing the input voltage level. The IC was implemented in a standard 28-nm CMOS process, and post-layout simulation results for the IC demonstrated that the rectifier operates at −8 dBm to 20 dBm and shows a maximum efficiency of 66 % for an input power from −4 to 20 dBm. The DC-DC converter outputs a voltage of 1.6∼2.2 V for a wide input voltage range of 1.2∼5 V and shows a power conversion efficiency of up to 80 %. For the entire IC, the maximum efficiency is 50.8 % at an input power of 12 dBm.

A Design of a Thermoelectric Energy Harvester for Minimizing Sensor Module Cost

This paper discusses a relationship between thermoelectric generator (TEG) electrical parameters, power efficiency of converters, and power consumption of loads in autonomous sensor modules. Based on the method discussed, one can determine the total number of TEG units together with the number of TEG arrays and the number of TEG units connected in series per array when the characteristics of TEG unit, the minimum temperature difference in operation, the power conversion efficiency of the converter and the load condition are given. A practical design flow to minimize TEG cost is proposed and demonstrated, taking the maximum open circuit voltage of TEG and the dependence of the power conversion efficiency of the converter on the input voltage of the converter into consideration. The entire system including TEG and a Dickson charge pump converter, which were designed through the proposed flow, was validated with SPICE.

The Dickson Charge Pump as a Signal Amplifier

In this paper it is proposed and explored the use of the Dickson charge pump (CP) to amplify time-variant signals. The study has been carried out through a theoretical analysis that provides an in-depth comprehension of the behavioral equations and the main design metrics commonly used to evaluate the performance of amplifiers. Starting from the analytical models, we show the conditions upon which the CP can be modeled with an equivalent small signal circuit and can amplify a signal. Then, assuming the CP working in the widest operative conditions, small-signal, large-signal and noise analysis are carried out. The results have been validated by extensive simulations and measurements on a proof of concept using a 130 nm CMOS technology.

Signal Amplification by Means of a Dickson Charge Pump: Analysis and Experimental Validation

Recently, with the aim of extending the use of the CP in all those applications where a time-variant signal must be amplified with its DC component above the positive power supply rail, the signal amplification feature of a conventional Dickson charge pump (CP) has been investigated, introducing a small-signal model for each particular condition in which a CP can work. In this paper this idea is further investigated, especially under the slow switching limit (SSL) condition, and experimental validation has been carried out using a 65 nm CMOS technology for four different voltage gain values. Starting from an equivalent model of the CP, the main small- and large-signal parameters are analytically derived and discussed in depth. As a proof of concept, experimental measurements on four CPs with different numbers of stages confirm the validity of this unconventional application and the effectiveness of the CP when used as an amplifier.

A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface Circuit With Cold Startup and Fast-Searching ZCD

This article presents an auto-polarity thermoelectric energy-harvesting interface circuit based on a single-inductor boost/buck–boost hybrid converter. The power stage is configured automatically as a boost converter for a positive input voltage or a buck–boost converter for a negative input voltage. A collaborative efficiency-improving scheme of frequency selection and maximum power point tracking (MPPT) is implemented for input power ranging from 1 to 800 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> . An improved digital zero-current detection (ZCD) technique with fast searching is proposed to turn off power switches accurately. Dual-polarity cold startup is realized with the aid of a pair of cross-coupled Dickson charge pumps. This work is fabricated with a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. From the measured results, the interface starts up from a 140- or −160-mV thermoelectric generator (TEG) voltage. It boosts input voltages ranging from 10 mV to 0.4 V and from −10 mV to −0.4 V to a 1.2-V output voltage. It achieves a peak end-to-end efficiency of 90% with a 0.3-V input voltage or 88% with a −0.4-V input voltage. Moreover, end-to-end efficiencies are higher than 80% for input voltages from 90 mV to 0.4 V and from −110 mV to −0.4 V.

A Compact Ultra-Broadband RF Rectifier Using Dickson Charge Pump

In this letter, an ultra-broadband rectifier is proposed and tested to get more RF energy from ambient. The rectifier using the Dickson charge pump increases the bandwidth and improves the dc voltage of the output load. The upper branch uses an inductor in series to counteract the capacitance of the imaginary parts of the diode and at the same time acts as a booster circuit to increase the output voltage. A shunt open-circuit stub acts as part of the matching network, tuning the imaginary part of the input impedance of the high frequency to realize the impedance matching of the ultra-broadband rectifier. The manufactured rectifier is measured and the result shows a fractional bandwidth of 145.5% (0.6-3.8 GHz) with an RF-to-dc power conversion efficiency (PCE) exceeding 40% at 8 dBm input power. And the measured efficiency remains over 50% across the frequency range from 1.6 to 3.4 GHz (including GSM1800, GSM2100, and WiFi). In addition, the rectifier made a maximum conversion efficiency of 66.6%.

Design of Miniaturized Incident Angle-Insensitive 2.45 GHz RF-Based Energy Harvesting System for IoT Applications

Using a license-free industrial, scientific, and medical (ISM) frequency band as 2.45 GHz, a miniaturized incident angle-insensitive radio frequency (RF) energy harvester design for the Internet-of-Things (IoT) applications is proposed. For incident angle insensitivity of ambient RF energy and a low-profile compact design, the proposed harvester is used to a two-layer printed circuit board (PCB) substrate, which consists of orthogonally deployed antennas with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$ </tex-math></inline-formula> balun, impedance matching, and Dickson charge pump circuits at each layer. The dual-polarized antenna for miniaturized design uses a bowtie-shaped meander dipole antenna having orthogonal arrangement. By measuring the efficiency of each diode stage of the rectifier circuit, a two-stage Dickson charge pump circuit with optimal efficiency was selected, and the dc outputs of the two rectifier circuits are connected in parallel. This rectifier circuit has a conversion efficiency of up to 71.4% and harvests approximately 1.6 times more power than a single-polarized circuit from any incident ambient RF signal. Due to its compact size and improved harvesting power at various incident angles, the proposed energy harvester can act as a power source, such as many kinds of ultralow power consumption systems, such as IoT sensors and medical applications.

A Resistor-Network Model of Dickson Charge Pump Using Steady-State Analysis

This paper presents a new average behavioral model, named a resistor-network (RN) model, that accurately predicts the electrical characteristics of the Dickson charge pump (DCP) circuit in the slow-switching limit and the fast-switching limit regions based on steady-state analysis. The RN model describes the steady-state behavior of a single-stage DCP using a network of resistors, which can then be cascaded to model N-stage DCP, taking into account the top- and bottom-plate parasitic capacitances. The RN model provides a comprehensive insight into various design parameters of the DCP, including the input/output current, output voltage, load characteristics, losses caused by parasitics, and power efficiency. Simulation results show that the proposed RN model accurately predicts the output voltage and power efficiency of the DCP over a wide range of switching frequencies, from 0.1 Hz to 1 GHz, with an error of less than 2% at the maximum power efficiency. The RN model provides designers with a simple and effective model to design DCP quickly and efficiently for a broad spectrum of applications, including energy harvesting and flash memory applications.

A Design of fast-setting on-chip Charge Pump Circuit

A circuit of fast-setting charge pump on-chip is designed based on the Dickson circuit. The charge pump circuit, which is improved, increases the initial node voltage. With the consideration of the current mismatch, the accurate clock of the duty circle below 50% is proposed. The HSPICE simulation result indicates that the setting time from 0V to 20V only needs 51.650μs for the charge pump, and it is faster than the traditional Dickson charge pump 26.03μs. In summary, the settling time of the output voltage of the charge pump is prominently decreased and the performance of the charge pump is obviously improved.

High Gain DC-DC Converter Integrating Dickson Charge Pump with Coupled Inductor Technique

In this paper, a novel high voltage gain DC-DC converter based on coupled inductor and voltage multiplier technique is proposed. The benefits of the proposed converter are ultra-high voltage gain, low voltage stress across the power switch and very low input current ripple by employing a low current ripple structure (LCR) at the input side. A low on state resistance (RDS(on)) of the power switch can be employed since the voltage stress is a maximum of 25% of the output voltage and the conduction losses of the switch is also reduced. Design of a 1.9kW, 48V at the low voltage side and 430V at the high voltage side is done and verified by simulation. Simulation results show an efficiency of over 93% when operating in continuous conduction mode (CCM).

A Self Threshold Voltage Compensated Rectifier for RF Energy Harvesting using 45nm CMOS Technology

A high frequency rectifier is the core of a RF energy harvesting system. It should offer a very good efficiency at low input power levels and to obtain that compensation of threshold voltage is a very important aspect. A threshold compensation scheme for MOSFETS for RF rectifier applicable in RF energy harvesting system is presented in this paper. The switching of the MOSFET is improved with overall enhancement of output rise time of the system. The design emphasis is to have a simplified circuit without the requirement of any external source so as to achieve self-sustainability in the true sense. The rectifier circuit is derived from the basic Dickson charge pump model and is evaluated using 45nm CMOS process. The design has utilized Metal Oxide Semiconductor Field Effect Transistor instead of basic diodes which ensures low power along with fabrication feasibility. The maximum measured PCE of the design is obtained to be 33% at 4dBm input power level at 500Mhz frequency with 1 Kilo Ohm load resistance. The output transient response rise time has been measured to be 85ns at 500MHz and 50.10ns at 1Ghz.

Transient Analysis of Energy Harvester for UHF Wireless Applications

In this letter, a detailed transient analysis is performed on a modified Dickson charge pump (CP) circuit, widely used as an energy harvester in radio frequency identification (RFID) and wireless sensor tags at ultrahigh frequency (UHF). An analytical model was developed and experimentally validated to capture the transient response of a multistage CP circuit at arbitrary capacitive and resistive load. The detailed analysis addresses the effect of stage number and matching network on steady-state dc voltage, efficiency, and charging rise time. The analysis shows that the steady-state voltage varies in proportionate to √(n) and the rise time varies in proportionate to n at no load condition, where n is the number of stages.

MOS capacitor based Dickson charge pump and ripple cancellation techniques using an LC circuit

This paper proposes a new architecture using integrated inductor and MOS capacitor based on Dickson charge pump associated with two parallel LC circuit after the first stage and output stage which cancel the ripple voltage that is generated in the output stage. In this circuit, the MOS capacitor as used instead of pumping capacitor, which helps in reducing the circuit Silicon area. Efficiency up to 80–90% can be achieved by reducing the parasitic effects and by using a MOS capacitor. The efficiency conversion and voltage gain increase or decreases depending on inductor and capacitor values. Vt drop loss is managed using high voltage clock. It shows that 3.5 V output voltage is generated from input voltage of 1.0 V with five stages of MOS capacitor (used as Pumping capacitor) in working frequency of 100 MHz the simulations were performed in Cadence Virtuoso platform with 0.18 μm CMOS process.

Fully-Integrated Dickson Converters for Single Photon Avalanche Diode Arrays

This article presents a novel low EMI technique to regulate the output voltage of fully-integrated switched capacitor Dickson type step-up DC/DC converters for SPAD arrays implemented in the Silterra 0.13 $\mu \text{m}$ HV-CMOS process. SPAD sensors are extremely sensitive to EMI and therefore require careful biasing. This design utilises current sources to limit the current flow into the flying capacitors altering the converter ratio and reduces the discontinuous pulse currents associated with capacitive converters. A variable voltage-controlled reference current enables output voltage regulation. The proposed four stage converter boosts 3.3 V up to an adjustable 15 V output voltage. A typical Dickson converter regulated by frequency control and the proposed current controlled converter were designed and manufactured to compare performance. Measurements confirm that the proposed design reduces the output ripple by more than 2 V when compared to the typical converter. The inclusion of the proposed voltage regulation technique reduces EMI which enables this fully-integrated Dickson charge pump to bias sensor arrays where the noise typically produced by these converters currently restricts or prohibits their use.

High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area

A hybrid charge pump was developed in a 0.13- μm Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage.

Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS

This article demonstrates a digitally friendly time-based analog-to-digital converter (ADC) exploiting Dickson charge-pump (CP) as part of a voltage-to-time conversion (VTC) implemented in 28-nm CMOS. In the proposed technique, the Dickson CP generates a ramp signal that is compared with the input voltage to generate a pulse of commensurable widths, which is then fed to a D-type flip-flop (DFF)-based time-to-digital converter (TDC). The TDC is composed of CMOS DFFs and digital circuits for digital conversion without any use of analog-intensive circuits, e.g., amplifiers or current sources. Thanks to the robustness of Dickson CP characteristics, the digital outputs of the proposed ADC can be corrected through a low-complexity deterministic digital mapping with improvements of 1.5-bit in peak effective number of bits (ENOB) and 9 dB in peak signal-to-noise-and-distortion ratio (SNDR) verified over three measured sample prototypes.