Silicon Devices Research Articles

785-nm Frequency Comb-Based Time-of-Flight Detection for 3D Surface Profilometry of Silicon Devices

Three-dimensional integrated circuits (3D-ICs) are becoming more significant in portable devices, autonomous vehicles, and data centers. As the demand for highly integrated and high-performance semiconductor devices grows, recent 3D integration technologies focus on lowering the size of the micro-structures on such devices for high density. In order to inspect the 3D semiconductor devices, it is critical to measure the heights, depths, and overall surface profiles of the micro-structures made with silicon materials. Here, we demonstrate precise surface imaging for silicon devices by using a femtosecond mode-locked laser centered at 785 nm wavelength and an electro-optic sampling-based time-of-flight detection method with sub-10-nanometer axial precision. We could successfully measure the surface profiles as well as the step heights of silicon wafer stacks and micro-scale structures on silicon substrates.

Optimisation of geometric aspect ratio of thin film transistors for low-cost flexible CMOS inverters and its practical implementation

A low-cost, flexible processor is essential to realise affordable flexible electronic systems and transform everyday objects into smart-objects. Thin film transistors (TFTs) based on metal-oxides (or organics) are ideal candidates as they can be manufactured at low processing temperatures and low-cost per unit area, unlike traditional silicon devices. The development of complementary metal–oxide–semiconductor (CMOS) technology based on these materials remains challenging due to differences in performance between n- and p-type TFTs. Existing geometric rules typically compensate the lower mobility of the metal-oxide p-type TFT by scaling up the width-to-length (W/L) ratio but fail to take into account the significant off-state leakage current. Here we propose the concept of an optimal geometric aspect ratio which maximises the inverter efficiency represented by the average switching current divided by the static currents. This universal method is especially useful for the design of low-power CMOS inverters based on metal-oxides, where the large off-current of the p-type TFT dominates the static power consumption of the inverter. We model the inverter efficiency and noise margins of metal-oxide CMOS inverters with different geometric aspect ratios and compare the performance to different inverter configurations. The modelling results are verified experimentally by fabricating CMOS inverter configurations consisting of n-type indium-silicon-oxide (ISO) TFTs and p-type tin monoxide (SnO) TFTs. Notably, our results show that reducing W/L of metal-oxide p-type TFTs increases the inverter efficiency while reducing the area compared to simply scaling up W/L inversely with mobility. We anticipate this work provides a straightforward method to geometrically optimise flexible CMOS inverters, which will remain relevant even as the performance of TFTs continues to evolve.

Tunnel-FET Evolution and Applications for Analog Circuits

In this work different generations of field effect tunneling transistor (TFET) are evaluated through DC digital and analog figures of merits. For TFET devices the main digital figure of merit is the subthreshold slope (SS), while for analog application the intrinsic voltage gain (AV) is the most important one. For the early generations, that are based on silicon, the SS does not reach values smaller than 60mV/dec at room temperature, however, the AV reaches values up to 80 dB, showing to be promising for analog applications. As the TFETs were being optimized for digital applications and consequently presenting better switching performance, the intrinsic voltage gain moves in the opposite direction. This opposite trend is related to which transport mechanism is predominant for each type of device. While III-V TFETs are more dependent on Band to Band Tunneling (BTBT), silicon devices are more relying on Trap-Assisted Tunneling (TAT). While BTBT allows for faster switching, TAT is less dependent on the drain electric field, so the former favors SS while the latter favors AV. Based on the good analog behavior of silicon channel TFETs, a two-stage operational transconductance amplifier (OTA) was designed with different TFET technologies and the compared results were discussed.

Hybrid aluminum nitride and silicon devices for integrated photonics

Aluminum nitride has advantages ranging from a large transparency window to its high thermal and chemical resistance, piezoelectric effect, electro-optic property, and compatibility with the complementary metal-oxide-semiconductor fabrication process. We propose a hybrid aluminum nitride and silicon platform for integrated photonics. Hybrid aluminum nitride-silicon basic photonic devices, including the multimode interferometer, Mach-Zehnder interferometer, and micro-ring resonator, are designed and fabricated. The measured extinction ratio is > 22 dB and the insertion loss is < 1 dB in a wavelength range of 40 nm for the Mach-Zehnder interferometer. The extinction ratio and intrinsic quality factor of the fabricated micro-ring resonator are > 16 dB and 43,300, respectively. The demonstrated hybrid integrated photonic platform is promising for realizing ultralow-power optical switching and electro-optic modulation based on the piezoelectric and electro-optic effects of aluminum nitride thin films.

Implementation of the electron track-structure mode for silicon into PHITS for investigating the radiation effects in semiconductor devices

In order to elucidate the mechanism of radiation effects in silicon (Si) devices, such as pulse-height defects and semiconductor soft errors, we developed an electron track-structure model dedicated to Si and implemented it into particle and heavy ion transport code system (PHITS). Then, we verified the accuracy of our developed model by comparing the ranges and depth-dose distributions of electrons in Si obtained from this study with corresponding experimental values and other simulated results. As an application of the model, we calculated the mean energies required to create an electron–hole pair in crystalline Si. Our calculated result agreed with the experimental data when the threshold energy for generating secondary electrons was set to 2.75 eV, consistent with the corresponding data deduced from past studies. This result suggested that the improved PHITS can contribute to the precise understanding of the mechanisms of radiation effects in Si devices.

Optical absorption from boron-containing quantum dot structures

This work studies optical absorption in the zinc-blende boron-containing quantum dot (QD) structures. Eight structures are studied; two of them are the ternary BInP/GaP and BInP/BP. The others are BGaAsP/BP, BAlAsP/BAs, BInAsP/InP, BGaInAs/GaAs, BGaInP/BP, and BInAsP/GaP. The emission wavelengths of the structures cover a broad spectrum range from UV to near-infrared. The structures with BAs and BP barriers emit at 227,292nm. The structures BInAsP/InP and BGaInAs/GaAs have peak absorptions at 870nm and 920nm wavelengths, while ternary and quaternary structures with GaP barrier are at 720 and 1200nm. The structures with GaP barrier have importance in silicon device technology. The absorption peaks are arranged where the smallest energy difference between the transition subbands correspond to a higher absorption peak and are associated with a wide bandgap energy difference between the barrier and QD. For boron increment by 0.005 in the QD region, the peak absorption of BInP/GaP and BInP/BP in the TE mode have a wider red-shift (170 nm) in the peak wavelength. BGaAsP/BP has an absorption peak four orders higher than BAlAsP/BP. For of BInAsP/InP QD structure, the absorption spectrum is increased by more than four times under 0.0001-mole fraction increment of boron.

Parametric Generation of Variable Spot Arrays Based on Multi-Level Phase Modulation

Holographic generation of beam spot array with high uniformity have been extensively investigated while existing methods cannot combine high quality and tunability. This paper demonstrated a method to generate beam spot array by using phase-only liquid crystal on silicon (LCOS) device. The proposed method is highly flexible and tolerant to the defects within the LCOS device. The uniformity deviation of the speckle array can be limited to within ±5% in the numerical simulation and the experimental results agreed well with the simulation results.

Silicene: an excellent material for flexible electronics

The outstanding properties of graphene have laid the foundation for exploring graphene-like 2D systems, commonly referred to as 2D-Xenes. Among them, silicene is a front-runner due to its compatibility with current silicon fabrication technologies. Recent works on silicene have unveiled its useful electronic and mechanical properties. The rapid miniaturization of silicon devices and the useful electro-mechanical properties of silicene necessitate the exploration of potential applications of silicene flexible electronics in nano electro-mechanical systems. Using a theoretical model derived from the integration of ab initio density-functional theory and quantum transport theory, we investigate the piezoresistance effect of silicene in the nanoscale regime. As with graphene, we obtain a small value of the piezoresistance gauge factor (GF) of silicene, which is sinusoidally dependent on the transport angle. The small GF of silicene is attributed to its robust Dirac cone and strain-independent valley degeneracy. Based on the obtained results, we propose to use silicene as an interconnect in flexible electronic devices and as a reference piezoresistor in strain sensors. This work will hence pave the way for exploring flexible electronics applications in other 2D-Xene materials.

Aging investigation of the latest standard dual power modules using improved interconnect technologies by power cycling test

The latest standard “New Dual” power module has been developed for both silicon and silicon-carbide devices to meet the increasing demands in high reliability and high temperature power electronic applications. Due to the new package is just starting to release on the market, the reliability performance has not been fully studied. This paper investigates the power cycling capabilities of a 1.7 kV/1.8 kA IGBT power module based on the new package. Both the electrical and thermal performances have been studied before and after the power cycling. Neither the chips nor bond wires have noticeable degradation after 1.2 million cycles with ΔTj = 100 K and Tjmax = 150 °C. Nevertheless, the end-of-life criterion of an increased conduction voltage (Vce) in the test environment has been reached at about 600 k cycles. The further scanning acoustic microscopy test unveils that the fatigue site shifts from the conventional near-to-die interconnect (e.g., bond wire lift-offs) to the direct bond copper (DBC) substrate and baseplate layers. Considering the new package has more than ten times cycle life than the traditional power module, it expects the thermo-mechanical fatigue is not the life-limiting mechanism with further improved interconnect technologies. Meanwhile, as the previous bottlenecks (e.g., bond wires) are addressed, some new fatigue mechanisms, e.g., delamination of the DBC, become visible in this new package.

In-Situ Study of Dynamics of Refractive Index Changes in Silicon Devices Induced by UV-light Irradiation

Silicon photonics has been studied in various areas by providing small-footprint, high-performance, and mass-producible optoelectronic components integrated on a chip. For the photonic packaging, ultraviolet (UV) curing techniques have been widely utilized. Meanwhile, silica cladding absorption to UV light could alter its refractive index (RI), affecting the optical testing of silicon devices during or after the device packaging. Therefore, it is significant to characterize the dynamics of RI changes induced by UV-light irradiation. However, the in-situ characterization of such devices is seldom explored. Here, we studied the influence of UV-light irradiation on silicon photonic devices by probing resonant wavelength shifts of a racetrack microring resonator. Specifically, we studied the temporary variation of the resonant wavelength and its recovery time under different UV-light exposure durations. Experimental results show that with a UV energy of 21 J/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the resonator had a maximum resonant wavelength shift of 0.31 nm, corresponding to an effective RI change of 0.0009 and recovering time of 95 minutes. Based on the experimental results, we compressively analyzed and compared RI changes induced by plasmon dispersion effect, thermal optical effect and photon-induced silica densification effect. Our study is expected to provide useful guidelines for in-situ silicon photonic testing and packaging.

Characterisation of irradiated and non-irradiated silicon sensors with a table-top two photon absorption TCT system

A tabletop Two Photon Absorption-Transient Current Technique (TPA-TCT) set-up built at CERN was used to investigate a non-irradiated PIN diode, an irradiated PIN diode, and a non-irradiated 5 × 5-multipad HPK LGAD. The intrinsic three dimensional spatial resolution of this method is demonstrated under normal incidence of the laser probe. A charge collection versus depth profile of the non-irradiated PIN diode is presented, where reflection on the rear silicon-air interface was observed. It is found that the time-over-threshold versus depth profile is particularly suitable to determine the boundaries of the DUT’s active volume. A depth scan of the irradiated PIN diode is discussed and a method to omit the single photon absorption background is presented. Finally, a charge collection measurement in the inter-pad region of the 5 × 5-multipad HPK LGAD is presented and it is demonstrated that TPA-TCT can be used to image the implantation and the electric field of segmented silicon devices in a three dimensional manner.

Low‐Temperature Photoluminescence Investigation of Light‐Induced Degradation in Boron‐Doped CZ Silicon

Light‐induced degradation (LID) in boron‐doped Czochralski grown (CZ) silicon is a severe problem for silicon devices such as solar cells or radiation detectors. Herein, boron‐doped CZ silicon is investigated by low‐temperature photoluminescence (LTPL) spectroscopy. An LID‐related photoluminescence peak is already found while analyzing indium‐doped p‐type silicon samples and is associated with the ASi–Sii defect model. Herein, it is investigated whether a similar peak is present in the spectra of boron‐doped p‐type CZ silicon samples. The presence of change in the photoluminescence signal intensity due to activation of the boron defect is investigated as well. Numerous measurements on boron‐doped samples are made. For this purpose, samples with four different boron doping concentrations are analyzed. The treatments for activation of the boron defect are based on the LID cycle. During an LID cycle, an additional peak or shoulder neither in the areas of the boron‐bound exciton transverse acoustic and nonphonon‐assisted peaks (BTA, BNP) nor in the area of the boron‐bound exciton transverse optical phonon‐assisted peak (BTO) is found. The defect formation also does not lead to a lower photoluminescence (PL) intensity ratio BTO(BE)/ITO(FE).

All laser-based fabrication of microchannel heat sink

Microchannel heat sinks have been recognized as efficient cooling platforms for thermal management of miniaturized devices because of their compact structure. Unlike most microfabrication processes, laser micromachining is a versatile direct writing method to rapidly produce microchannels in brittle substrates such as silicon wafers. In this study, an all-laser fabrication method is proposed to fabricate a microfluidic heat sink for silicon devices. Lasers are used for engraving microchannels on a silicon wafer, drilling inlet/outlet holes in quartz glass cover, and welding the Si sample and quartz glass cover. The entire fabrication process is completed within two hours. The microchannel surface is converted into a hydrophilic wall as proven by contact angle measurement, and a water flow is easily introduced to the channel as a cooling fluid. The boiling heat transfer performance of the fabricated microfluidic channel is evaluated by applying heat to the bottom of the device. A micro-heater placed underneath the Si substrate is also prepared using a laser to induce selective sintering of a conductive Ag layer. The heat generated by the heater is successfully removed by boiling heat transfer, and the critical heat flux is measured to be ∼ 55.2 W/cm2 at a water flux of 208 kg/m2s.

Material Properties of a Low Contraction and Resistivity Silicon–Aluminum Composite for Cryogenic Detectors

We report on the cryogenic properties of a low-contraction silicon–aluminum composite, namely Japan Fine Ceramics SA001, to use as a packaging structure for cryogenic silicon devices. SA001 is silicon–aluminum composite material (75% silicon by volume) and has a low thermal expansion coefficient ( $$\sim $$ 1/3 that of aluminum). The superconducting transition temperature of SA001 is measured to be 1.18 K, which is in agreement with that of pure aluminum and is thus available as a superconducting magnetic shield material. The residual resistivity of SA001 is 0.065 µΩm, which is considerably lower than equivalent silicon–aluminum composite material. The measured thermal contraction of SA001 immersed in liquid nitrogen is $$\frac{L_{293\,\mathrm {K}}-L_{77\,\mathrm {K}}}{L_{293\,\mathrm {K}}}=0.12\%$$ , which is consistent with the expected rate obtained from the volume-weighted mean of the contractions of silicon and aluminum. The machinability of SA001 is also confirmed with a demonstrated fabrication of a conical feedhorn array, with a wall thickness of 100 µm. These properties are suitable for packaging applications for large-format superconducting detector devices.

Series of ultra-low loss and ultra-compact multichannel silicon waveguide crossing.

Ultra-compact waveguide crossing (UC-WC) is a basic component in optoelectronic fusion chip solutions, as its footprint is smaller in the orders of magnitude than that of traditional photonic integrated circuits (PICs). However, a large loss of UC-WC (decibel level) becomes a barrier to scaling and practicality. Here, we propose a series of ultra-low loss UC-WC silicon devices using an advanced hybrid design that combines the adjoint method with the direct binary search (DBS) algorithm. Simulation results show that our 2 × 2 UC-WC has an insertion loss as low as 0.04 dB at 1550 nm, which is about ten times lower than the previous UC-WC results. In the valuable C-band (1530-1565 nm), the insertion loss of UC-WC is lower than -0.05 dB, and the channel crosstalk is lower than -34 dB. Furthermore, for the 3 × 3 UC-WC device, the highest insertion loss in the entire C-band is approximately -0.07 dB, and the highest channel crosstalk is lower than -33 dB. Additionally, the 4 × 4 and more complex 8 × 8 UC-WC devices were also analyzed. The highest insertion loss for 4 × 4 and 8 × 8 UC-WC in the C-band is only -0.19 dB and -0.20 dB, respectively, and the highest channel crosstalk is approximately -22dB and -28 dB, respectively. These results confirm that the designed devices possess two attractive features simultaneously: ultra-compactness and ultra-low insertion loss, which may be of great value in future large-scale optoelectronic fusion chips.

Atomic Force Microscope Characterization of the Bending Stiffness and Surface Topography of Silicon and Polymeric Electrodes.

Implanted electrodes in the brain are increasingly used in research and clinical settings to understand and treat neurological conditions. However, a foreign body response typically occurs after implantation, and glial encapsulation of the device is a commonly observed. Multiple factors affect how gliosis surrounding the implantable electrodes evolves. Characterizing and measuring the surface features and mechanical properties of these devices may allow us to predict where gliosis will occur, and understanding how electrode design features may impact astrogliosis may give researchers a set of design guidelines to follow to maximize chronic performance. In this study, we used atomic force microscopy to measure surface roughness on parylene, polyimide, and silicon devices. Multiple features on microelectrode arrays were measured, including electrode sites, traces, and the bulk substrate. We found differences in surface roughness according to device material, but not device features. We also directly measured the bending stiffness of silicon devices, providing a more exact quantification of this property to corroborate calculated estimates.

Circuit-Based Electrothermal Modeling of SiC Power Modules With Nonlinear Thermal Models

Silicon carbide (SiC) power devices have the potential to operate at high temperatures beyond the capabilities of silicon power devices. At increased temperatures, the temperature-dependent material properties of the SiC die and the package multilayer structure can influence the electrothermal (ET) device performance. In this article, a new step-back-correction technique implemented in a finite-difference-method-based thermal modeling tool is proposed to reduce the computational cost while maintaining a good accuracy of ET simulations for multichip power modules. The simulations take the temperature dependence of the thermal conductivity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$k(T)$</tex-math></inline-formula> and both conduction and switching losses into account. The importance of considering <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$k(T)$</tex-math></inline-formula> for the accurate temperature prediction of SiC power devices is demonstrated for thermal impedance evaluations characterized by high-temperature swings, as well as for a 100-kHz boost converter with low device temperature amplitudes in the steady state. The proposed ET modeling is validated by COMSOL simulations and infrared camera measurements on an example of a custom-designed and custom-manufactured half-bridge SiC power module.

Wideband PPT Class $\Phi _2$ Inverter Using Phase-Switched Impedance Modulation and Reactance Compensation

Class <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\Phi _2}$</tex-math></inline-formula> is a suitable power amplifier (PA) topology for applications that demand low device voltage stress and simple gate driving. The push–pull with T network (PPT) version of this architecture can be advantageous over a conventional single-ended <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\Phi _2}$</tex-math></inline-formula> due to higher power capabilities through interleaving and simple closed-form design equations. The downside with this and many other switch-mode PAs is that they perform efficiently only at a single frequency with the power degrading outside the nominal point of operation. To improve upon this issue, we incorporate a phase-switched impedance modulation variable capacitor and a reactance compensation network so that the PPT <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\boldsymbol{\Phi _2}$</tex-math></inline-formula> can function across broadband. We experimentally demonstrate a 300-W PA for a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\Omega }$</tex-math></inline-formula> load impedance using silicon devices. The PA achieves above 90% efficiency over approximately a 30% fractional bandwidth. The PA can also operate across broadband with light loads, where above 80% efficiency is maintained for up to five times higher load resistances. This switch-mode PA is one of the first to demonstrate such performance under load variation and across a wide bandwidth.

Edge Terminations for 4H-SiC Power Devices: A Critical Issue

Edge termination is a critical part of a power devices. Numerous edge termination types have been developed for silicon devices. Implementation of these termination architectures are not straightforward in SiC due to physical and processing specificities: lower junction depths, higher electric field, trench depth and shaping limitations, etc. Two main families of terminations are currently used in commercial devices, pure Field Guard Rings, and JTE + Rings combination. The increasing number of trench commercial devices requires new approaches based on etched rings filled with dielectrics or polysilicon. For epitaxied bipolar devices, MESA with bevel angle termination combined with JTE based architecture are also suitable. In any case, and especially regarding avalanche capability requirements, not only the termination architecture is relevant, but also the passivation type, the channel stopper design, the 3D design. As modelling using conventional tools is not fully reliable, specific complementary characterization methods are needed. For instance, micro-OBIC can be very effective to determine the electric field distribution in the periphery of the power devices.

Study of Photocarriers Lifetime Distribution in a‐Si:H via Magneto‐photoconductivity and Magneto‐Photoluminescence

AbstractHerein, the magneto‐photoluminescence (MPL) of localized photocarriers and magneto‐photoconductivity (MPC) of delocalized photocarriers in amorphous hydrogenated silicon (a‐Si:H) films and devices, respectively, are investigated. Both responses are caused by mixing of spin sublevels in the photogenerated electron–hole (e–h) pairs that alters their recombination and dissociation rates. The spin mixing occurs by a combination of hyperfine interaction (HFI) between spin ½ photocarriers and neighboring 29Si and 1H nuclei, and the Δg mechanism which originates from a difference in the Landé g‐factors of electrons and holes. The existing disorder in a‐Si:H films leads to dispersive field response that is described by a unique dispersive parameter α &lt; 1, from which the e–h lifetime distribution, g(τ) is obtained. The mean e–h lifetime is found to be ≈12 ns for the high‐energy, relatively delocalized photocarriers generating the photocurrent, as compared to ≈200 ps for the lower energy, trapped e–h pairs which yield photoluminescence. The MPL(B) and MPC(B) responses in a‐Si:H subjected to prolonged illumination that causes Staebler–Wronski type degradation, and subsequent annealing are studied. The illumination‐induced photocarrier localization that enhances the HFI component is found, which dramatically decreases upon annealing; this method can assess optoelectronic device degradation.