Device Transconductance Research Articles

Ultra-sensitive nitrate-ion detection via transconductance-enhanced graphene ion-sensitive field-effect transistors

Current potentiometric sensing methods are limited to detecting nitrate at parts-per-billion (sub-micromolar) concentrations, and there are no existing potentiometric chemical sensors with ultralow detection limits below the parts-per-trillion (picomolar) level. To address these challenges, we integrate interdigital graphene ion-sensitive field-effect transistors (ISFETs) with a nitrate ion-sensitive membrane (ISM). The work aims to maximize nitrate ion transport through the nitrate ISM, while achieving high device transconductance by evaluating graphene layer thickness, optimizing channel width-to-length ratio (RWL), and enlarging total sensing area. The captured nitrate ions by the nitrate ISM induce surface potential changes that are transduced into electrical signals by graphene, manifested as the Dirac point shifts. The device exhibits Nernst response behavior under ultralow concentrations, achieving a sensitivity of 28 mV/decade and establishing a record low limit of detection of 0.041 ppt (4.8 × 10−13 M). Additionally, the sensor showed a wide linear detection range from 0.1 ppt (1.2 × 10−12 M) to 100 ppm (1.2 × 10−3 M). Furthermore, successful detection of nitrate in tap and snow water was demonstrated with high accuracy, indicating promising applications to drinking water safety and environmental water quality control.

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

3D FinFETs are meticulously scaled down to sub-14 nm leading to reemerging undesirable characteristics namely increased Drain Induced Barrier Leakage (DIBL), higher subthreshold swing and excessive leakage currents. This inhibits the scaling of FinFETs and research suggests probable utilization of strained silicon technology in FinFETs to improve the on currents and transconductance of the nano devices. The emergence of quantum effects including velocity overshoot and carrier confinement severely affects the electrical characteristics at sub-10 nm channel length devices. Therefore, amalgamation of strained silicon prove to be a boon in FinFETs while being at par with the proposed 3 nm technology node of IRDS 2018, and designing to develop reliable devices at 08 nm gate length is the requisite. Thus, exploring the design and performance investigation of novel 08 nm Quantum Well FinFETs (QW-FinFETs) incorporating a tri-layered strained silicon Heterostructure-On-Insulator (HOI)are proposed with distinct channel dimensions which are analyzed and compared with existing devices. The optimum QW-FinFET device developed for 3 nm technology node of IRDS 2018 achieved a ∼25% enhancement in drain currents with Device D2 portraying almost ∼103% escalations in electron mobility on account of ballistic transport of charge carriers without scattering and enriching the performance for the future generation of device resulting in faster switching operation in sub-nano regime.

Exploration of underlap induced high-k spacer with gate stack on strain channel cylindrical nanowire FET for enriched performance

This research explores a comprehensive examination of gate underlap incorporated strained channel Cylindrical Gate All Around Nanowire FET having enriched performances above the requirement of the 2 nm technology node of IRDS 2025. The device installs a combination of strain engineering based quantum well barrier system in the channel region with high-k spacers sandwiching the device underlaps and stack high-k gate-oxide. The underlaps are prone to parasitic resistance and various short channel effects (SCEs) hence, are sandwiched by HfO2 based high-k. This SCE degradations and a strong electric field in the drain-channel region is rendered controlling the leakages. The strain based Nanosystem engineering is incorporated with Type-II heterostructure band alignment inducing quantum well barrier mechanism in the ultra-thin cylindrical channel region creating an electrostatic charge centroid leading to energy band bending and splitting among the two-fold and four-fold valleys of the strained Silicon layer. This provides stupendous electron mobility instigating high current density and electron velocity in the channel. Thereby, the device is susceptible to on-current enhancement via ballistic transport of carriers and carrier confinement via succumbing of quantum charge carriers. The device transconductance, Ion, Ioff, Ion/Ioff ratio are measured and the output performance (ID-VDS) characteristics is determined providing emphatic enrichments in contrast to the existing gate all-around FETs as well as the 2 nm technology node data of IRDS 2025. Hence, the strained channel Nanowire FET device developed here is presented here as the device of the future for various digital applications, RF applications and faster switching speed.

(Invited) Gallium Oxides Devices for Grid-Scale Power Electronics and High Power Switched Mode RF Amplifiers

Within a decade of the first demonstration of a MESFET device, monoclinic β-Ga2O3 (Ga2O3) devices have made incredible progress in breakdown voltages, power device figure of merit and high-speed performance. It has emerged as a promising ultra-widebandgap semiconductor for next generation power, GHz switching and RF applications. In this talk, we will present an overview of our studies on fundamental transport properties, kilovolt class power MOSFETs and aggressively scaled RF devices. The large bandgap of Ga2O3 leads to a high critical field strength. This high field strength in combination with demonstrated room temperature mobility and calculated electron velocity leads to a higher Baliga’s Figure of Merit (BFoM) and Johnston Figure of Merit (JFoM) than current commercially available widebandgap technologies. Additionally, the large bandgap also enables high temperature operation and radiation hardness making it attractive for space applications such as Mars and Venus missions.In the first part, we will discuss the deep insights gained from the first-principles based transport calculations in Ga2O3. We will discuss the limits to low field mobility, saturation velocities and impact ionization coefficients. The impact of the plasmon-phonon coupling on the phonon limited transport will be discussed. We will present the experimental signatures of plasmon-phonon coupling and anti-screening behavior in ionic gated accumulation layers.Next, I will describe our work on the lateral MOSFETs with improved field plate design and beyond-kV breakdown. Temperature dependent analysis and device simulation suggest an extrinsic breakdown mechanism outside the channel. A simple and yet effective SU-8 polymer passivation technology was developed that results in significant improvement in breakdown voltages. The higher field strength of the SU-8 polymer enables a significant increase in breakdown voltage to 8 kVs in lateral MOSFETs. However, these devices show a high Ron, which is due to the depletion caused by RIE of the channel. We will present the use of ultra-high vacuum annealing techniques to improve the on-resistance of the devices still maintaining the multi-kilo-volt rating of the devices.Due to its high JFoM, Ga2O3 is a potential candidate for high power density RF amplifiers. We will also present the performance advancement that can be obtained in RF power performance using Ga2O3 technology. We will present the challenges in the technology and potential solutions. We will present the experimental DC and pulsed measurements on laterally scaled MOSFETs with 100 nm gate length. Severe DC-RF dispersion was observed which is attributed to the RIE damage and surface states on the oxide. Passivation of the devices shows reduced current collapse. Using aggressive gate lengths and gate-source spacing scaling, (AlxGa1-x)2O3/Ga2O3 heterostructure FETs were fabricated that show record high RF performance. The device transconductance was limited by the regrowth interface resistance. Ex-situ silicon nitride passivation was shown to be effective to reduce DC-RF dispersion. Recently, thin channel MOSFETs with deep-sub-micron gate lengths and source/drain regrowth have demonstrated devices with simultaneously low on resistance, high frequency, high voltages.

A high-performance doping-less tunnel FET with pocketed architecture: proposal and analysis

In this paper, we propose a doping-less dual-material double-gate tunnel field-effect transistor with a P+ pocket (PP-DMG TFET). This gate-engineered technique is typically used in a MOSFET to improve device performance. The P+ pocket is embedded at the source side to enhance the performance of the pocket-engineered PP-DMG TFET device. This paper compares the performance of four DG-TFET-based devices, i.e. single-material gate (SMG), single-material gate with P+ pocket (PP-SMG), dual-material gate (DMG), and dual-material gate with P+ pocket (PP-DMG), by using 2D simulations. Electrostatic doping based on the charge plasma concept forms the requisite n–i–p+ structure for tunneling formed on a thin intrinsic silicon layer. The proposed device (PP-DMG) has high ON-current capability, a high ON/OFF ratio and lower point subthreshold of 15.3 mV/dec, and an average subthreshold of 18.6 mV/dec. The analog parameters transconductance (gm) and cutoff frequency (fT) show impressive improvement. The device efficiency and transconductance frequency product (TFP) are also discussed. Finally, linearity and distortion analysis of parameters including VIP2, VIP3, IIP3, and IMD3 is carried out.

Study of Thin Barrier GaN Biosensor with Improved Sensitivity

The sensitivity of GaN biosensor device is directly related to transconductance (gm) of the HEMT device. In this paper, by applying with AlGaN/GaN material of thin AlGaN barrier and appropriately Al composition, the maximum transconductance (gm,max) is shifted near the zero gate voltage spontaneously. The sensitivity of the biosensor can be improved without gate reference electrode. The sensitivity of 0.35 mA/pH in pH detection and 1pg/ml in protein detection is achieved.

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process

In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dBΩ, a BW of 14.8 GHz, an input-referred noise of 33.6 pA/Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consume 49 mW and occupies an active area of 0.0076 mm2.

Quantitative Analysis on the Field Strength in the Addressable Gated ZnO Nanowire Field Emitter Arrays: Model and Experiment

Addressable gated field emitter arrays (FEAs) have important applications in vacuum microelectronic devices. To fabricate high-performance device, a comprehensive understanding on the field emission characteristics of gated FEAs is necessary, which requires a quantitative analysis method. In this work, a general model based on Fowler-Nordheim (FN) theory has been established to fulfill this blank. It is found that nonlinear FN plot with positive and negative slopes could occur in gated FEAs, which its turning point is related to the proportion of anode and gate field. This provides a way for obtaining the field strengths applied by the anode and gate structures. Besides, the transconductance of the gated FEAs increases exponentially with the total surface field, which indicates that both the anode and gate field need to be increased for achieving a high transconductance device. As a demonstration, the addressable gated ZnO nanowire FEAs using multimicrosize pattern with radius as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.5 ~\mu \text{m}$ </tex-math></inline-formula> have been designed and fabricated. The relationship between the transconductance and anode voltage can be well fitted by using the model, which deduces the proportion of anode and gate field in the device to be about 3:1.

Impact of Gamma Radiations on Static, Pulsed I–V, and RF Performance Parameters of AlGaN/GaN HEMT

In this article, the impact of gamma (<inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>) irradiation on passivated and unpassivated AlGaN/GaN HEMT is presented in detail. Passivated and unpassivated GaN-HEMT devices have been exposed to <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-radiations to a total dose of 10 kGy. Post-<inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation, a refinement in ohmic contact, which makes device source/drain, is recorded. Alteration in Schottky gate electrical characteristics (<inline-formula> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${I}\!\!-\!\!{V}$ </tex-math></inline-formula>) along with advances in device drain current and transconductance has been observed in unpassivated HEMT, while it remained almost unaltered in passivated GaN-HEMT after <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation. The OFF-state gate leakage has deterioration in both types of HEMTs, suggesting a modification in trap concentration beneath the gate and near gate region during <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-exposure. This is confirmed via pulsed <inline-formula> <tex-math notation="LaTeX">${I}\!-\!{V}$ </tex-math></inline-formula> measurements. A strong upswing in drain current recovery after stress bias is recorded post-<inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation in both types of HEMTs. This confirms that the trapping sites have been altered during <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-exposure. Possible reasons causing this modification are improvement in gate metal barrier inhomogeneities and reduction/rearrangement of crystal defects during <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula> <i>-exposure</i>. The effect of <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-radiation on intrinsic/extrinsic device parameters has also been determined using S-parameters measurements. Intrinsic/extrinsic device parameters of passivated HEMT are observed to be less affected by <inline-formula> <tex-math notation="LaTeX">$\gamma $ </tex-math></inline-formula>-irradiation in comparison to unpassivated GaN-HEMT devices, and post-radiation, both the devices have similar device parameters values as it was prior radiation making it suitable for harsh environment applications.

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

Enhancement of f MAX of InP-based HEMTs by double-recessed offset gate process

A double-recessed offset gate process technology for InP-based high electron mobility transistors (HEMTs) has been developed in this paper. Single-recessed and double-recessed HEMTs with different gate offsets have been fabricated and characterized. Compared with single-recessed devices, the maximum drain–source current (I D,max) and maximum extrinsic transconductance (g m,max) of double-recessed devices decreased due to the increase in series resistances. However, in terms of RF performance, double-recessed HEMTs achieved higher maximum oscillation frequency (f MAX) by reducing drain output conductance (g ds) and drain to gate capacitance (C gd). In addition, further improvement of f MAX was observed by adjusting the gate offset of double-recessed devices. This can be explained by suppressing the ratio of C gd to source to gate capacitance (C gs) by extending drain-side recess length (L rd). Compared with the single-recessed HEMTs, the f MAX of double-recessed offset gate HEMTs was increased by about 20%.

Are 2D Interfaces Really Flat?

Two-dimensional (2D) van der Waals materials are subject to mechanical deformation and thus forming bubbles and wrinkles during exfoliation and transfer. A lack of interfacial "flatness" has implications for interface properties, such as those formed by metal contacts or insulating layers. Therefore, an understanding of the detailed properties of 2D interfaces, especially their flatness under different conditions, is of high importance. Here we use cross-sectional scanning transmission electron microscopy (STEM) to investigate various 2D interfaces (2D-2D and 3D-2D) under the effects of stacking, atomic layer deposition (ALD), and metallization. We characterize and compare the flatness of the hBN-2D and metal-2D interfaces down to angstrom resolution. It is observed that the dry transfer of hexagonal boron nitride (hBN) can dramatically alter the interface structure. When characterizing 3D metal-2D interfaces, we find that Ni-MoS2 interfaces are more uneven and have larger nanocavities compared to other metal-2D interfaces. The electrical characteristics of a MoS2-based field-effect transistor are correlated to the interfacial transformation in the contact and channel regions. The device transconductance is improved by 40% after the hBN encapsulation, likely due to the interface interactions at both the channel and contacts. Overall, these observations reveal the intricacy of 2D interfaces and their dependence on the fabrication processes.

Strain-engineering in AlGaN/GaN HEMTs: impact of silicon nitride passivation layer on electrical performance

In this work, we present a physics-based analysis of two-dimensional electron gas (2DEG) sheet carrier density and other microwave characteristics such as transconductance and cutoff frequency of AlxGa1−xN/GaN high electron mobility transistors (HEMT). An accurate polarization-dependent charge control-based analysis is performed for microwave performance assessment in terms of current, transconductance, gate capacitances, and cutoff frequency of lattice-mismatched AlGaN/GaN HEMTs. The influence of stress on spontaneous and piezoelectric polarization is included in the simulation of an AlGaN/GaN HEMT. We have shown the change in threshold voltage (Vt) due to tensile and compressive strain with different gate lengths. Also, the influence of stress due to the change in nitride thickness is presented. Our simulation results for drain current, transconductance, and current-gain cutoff frequency for various gate length devices are calibrated and verified with experimental data over a wide range of gate and drain applied voltages, which are expected to be useful for microwave circuit design. The predicted transconductance, drain conductance, and operation frequency are quite close to the experimental data. The AlGaN/GaN heterostructure HEMTs with nitride passivation layers show great promise as a candidate in future high speed and high power applications.

Gamma-radiation Induced Degradation of the Electrical Characteristics of NMOSFETs

In this paper, we present the gamma-radiation induced degradation of the electrical characteristics of N-channel Metal Oxide Semiconductor Field Effect Transistors (NMOSFETs). The exposure was done with a 60Co gamma-ray source over the total dose range of 1 kGy to 10 kGy, with a dose rate of 3.9 kGyhr. The effects of irradiation induced degradation on device parameters such as threshold voltage, low field mobility, device transconductance (Gm), saturation drain current, off state leakage current and subthreshold swing were investigated. The threshold voltage was determined using the linear extrapolation method. The device dimensions with Wide/Long channel that excluded the Narrow Channel Effect (NCE) and the Short Channel Effect (SCE) were measured. The results showed that the threshold voltage, device transconductance and low field mobility decreased but the saturation drain current, off state leakage current and subthreshold swing increased as the gamma irradiation increased. Finally, the macro parameter models were investigated and discussed.

Analysis of Instability Behavior and Mechanism of E-Mode GaN Power HEMT with p-GaN Gate under Off-State Gate Bias Stress

In this study, we investigate the degradation characteristics of E-mode GaN High Electron Mobility Transistors (HEMTs) with a p-GaN gate by designed pulsed and prolonged negative gate (VGS) bias stress. Device transfer and transconductance, output, and gate-leakage characteristics were studied in detail, before and after each pulsed and prolonged negative VGS bias stress. We found that the gradual degradation of electrical parameters, such as threshold voltage (VTH) shift, on-state resistance (RDS-ON) increase, transconductance max (Gm, max) decrease, and gate leakage current (IGS-Leakage) increase, is caused by negative VGS bias stress time evolution and magnitude of stress voltage. The significance of electron trapping effects was revealed from the VTH shift or instability and other parameter degradation under different stress voltages. The degradation mechanism behind the DC characteristics could be assigned to the formation of hole deficiency at p-GaN region and trapping process at the p-GaN/AlGaN hetero-interface, which induces a change in the electric potential distribution at the gate region. The design and application of E-mode GaN with p-GaN gate power devices still need such a reliability investigation for significant credibility.

Realizing High-Performance β-Ga₂O₃ MOSFET by Using Variation of Lateral Doping: A TCAD Study

In this article, for the first time, a variation of lateral doping (VLD) technique was proposed to improve blocking voltage and ON-resistance properties in the lateral β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> metal-oxide-semiconductor field-effect transistor (MOSFET). Enhancement-mode operation was achieved in the VLD transistor. The maximum transconductance of this new device is more than three times as large as the uniformly doped (UD) transistor. Moreover, the OFF-state electric field at the channel was suppressed compared to the UD transistor, resulting in higher blocking voltage. We also investigated the optimal device properties with changing channel concentration in the drift region of VLD transistor. A power figure of merit of 332.7 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was reached by VLD design. Thus, this proposed structure provides a new design strategy for high-power β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> MOSFETs.

Influences of increasing gate stem height on DC and RF performances of InAlAs/InGaAs InP-based HEMTs* *Project supported by the National Natural Science Foundation of China (Grant No. 61434006).

The T-gate stem height of InAlAs/InGaAs InP-based high electron mobility transistor (HEMT) is increased from 165 nm to 250 nm. The influences of increasing the gate stem height on the direct current (DC) and radio frequency (RF) performances of device are investigated. A 120-nm-long gate, 250-nm-high gate stem device exhibits a higher threshold voltage (V th) of 60 mV than a 120-nm-long gate devices with a short gate stem, caused by more Pt distributions on the gate foot edges of the high Ti/Pt/Au gate. The Pt distribution in Schottky contact metal is found to increase with the gate stem height or the gate length increasing, and thus enhancing the Schottky barrier height and expanding the gate length, which can be due to the increased internal tensile stress of Pt. The more Pt distributions for the high gate stem device also lead to more obvious Pt sinking, which reduces the distance between the gate and the InGaAs channel so that the transconductance (g m) of the high gate stem device is 70 mS/mm larger than that of the short stem device. As for the RF performances, the gate extrinsic parasitic capacitance decreases and the intrinsic transconductance increases after the gate stem height has been increased, so the RF performances of device are obviously improved. The high gate stem device yields a maximum f t of 270 GHz and f max of 460 GHz, while the short gate stem device has a maximum f t of 240 GHz and the f max of 370 GHz.

Ion Exchange Gels Allow Organic Electrochemical Transistor Operation with Hydrophobic Polymers in Aqueous Solution.

Conjugated-polymer-based organic electrochemical transistors (OECTs) are being studied for applications ranging from biochemical sensing to neural interfaces. While new polymers that interface digital electronics with the aqueous chemistry of life are being developed, the majority of high-performance organic transistor materials are poor at transporting biologically relevant ions. Here, the operating mode of an organic transistor is changed from that of an electrolyte-gated organic field-effect transistor (EGOFET) to that of an OECT by incorporating an ion exchange gel between the active layer and the aqueous electrolyte. This device works by taking up biologically relevant ions from solution and injecting more hydrophobic ions into the active layer. Using poly[2,5-bis(3-tetradecylthiophen-2-yl) thieno[3,2-b]thiophene] as the active layer and a blend of an ionic liquid, 1-butyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide, and poly(vinylidene fluoride-co-hexafluoropropylene) as the ion exchange gel, four orders of magnitude improvement in device transconductance and a 100-fold increase in kinetics are demonstrated. The ability of the ion-exchange-gel OECT to record biological signals by measuring the action potentials of a Venus flytrap is demonstrated. These results show the possibility of using interface engineering to open up a wider palette of organic semiconductors as OECTs that can be gated by aqueous solutions.

(Invited) Band Line-up of High-k Oxides on GaN

GaN high electron mobility transistors (HEMTs) have been commercially available for over 10 years, however gate leakage limits their performance. The HEMT has the advantages of offering simple associated circuit design and fail-safe operation. Currently the GaN based Metal-Insulator-Semiconductor (MIS)-HEMT device is seen to demonstrate superior performance in power electronics applications over the Schottky gate counterpart, due to its inherently lower gate leakage current, together with the ability to provide larger forward gate voltage swing by engineering the threshold voltage between depletion and enhancement mode operation and also an improved gate-drain breakdown voltage. High band gap gate dielectric materials are preferable as they can provide higher tunnelling barriers for electrons and holes, which result in lower gate leakage current. On the other hand, high dielectric constant (high-k) material is also necessary for improved electrostatic control over the channel and improved on-current, which in-turn results in higher transconductance. The quality of the gate dielectric and the dielectric/GaN interface plays a central role in device performance due to potential problems arising from fixed oxide charge, border and interface traps. The leakage current issue has been mitigated using Al2O3, SiO2 and Si3N4, but comes at a cost of device transconductance degradation and undesirable threshold voltage shifts. A number of high-k dielectrics such as HfO2, ZrO2, Ta2O5, LaLuO3 and TiO2 have been investigated to resolve this issue.In this paper, engineered high-k oxide approach will be presented where Al2O3 is doped with Ti to boost oxide permittivity value while preserving band offsets, as well as Ga2O3 doped with Al to increase band gap and maintain good interface quality with GaN. X-ray photoelectron spectroscopy, inverse photoemission spectroscopy and variable angle spectroscopic ellipsometry were used to estimate the band alignment and interfacial properties. TiO2 is very attractive due to having reported k of 20-86 but has a small band gap of 3.4 eV for amorphous and 3.26 eV for anatase TiO2, being far too narrow to obtain a sufficient band offset with GaN of >1 eV. Al2O3 on the other hand has a sufficient band offset of 1.8-2 eV with AlGaN but suffers from a low dielectric constant of 7.5-9.6 depending on the growth method. The previous studies of Al2O3/TiO2 nanolaminates show favourable properties, in particular the optimum between the rather high-k (~30) and low leakage current has been observed for 30% Ti. No band offset study has been reported for TixAl1-xOy/GaN system. We will show full band alignment analysis of TixAl1-xOy/GaN fabricated by atomic layer deposition (ALD) on GaN for the range of Ti composition of up to 40%. Furthermore, a trivalent Ga2O3 is a promising oxide due to its band gap of 4.4 - 4.9 eV and a moderate permittivity of 10-14. Thermally oxidized Ga2O3 has shown valence band offset of 1.4 eV to GaN. A drawback of thermal oxidation is a growth of non-stoichiometric oxide at GaN interface reported to be as Ga(x+2)N3xO(3-3x). In contrast, ALD has been shown to produce Ga2O3 with no interfacial layer with GaN and low density of interface states of 3.62x1011 cm-2eV-1. Despite the good interface with GaN, the issue with using Ga2O3 is a small conduction band offset (< 1 eV) leading to high leakage current. In this paper, Al doped Ga2O3 have been fabricated using ALD on GaN. The results point to substantial increase of the band gap from ~4.6 eV for Ga2O3 to 5.9 eV for the 1:19 Ga:Al doped sample and a strong suppression of leakage current for Al doped Ga2O3 MIS capacitors. The results are of importance for future GaN HEMTs. Acknowledgement. The work has been conducted under the University Grants Commission - UK-India Education Research Initiative (UGC-UKIERI) joint research programme UKIERI III, project numbers IND/CONT/G/17-18/18 and F.No.184-1/2018(IC), titled “Dielectric engineering on GaN for sustainable energy applications” funded by the British Council. The authors also acknowledge UKRI GCRF GIAA award 2018/19 and “Digital in India” project no. EP/P510981/1, both funded by the EPSRC, UK.

Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

This article is discussing about threshold voltage roll off effect in Ultra Thin Fully Depleted Silicon on Insulator MOSFET. The device performance is improved due to the reduction in threshold voltage roll off. The thickness of oxide layer is optimized to 2nm which also have a vital role in improvement of device’s throughput. The effect of oxide thickness on parasitic parameter also discussed. Device conductance and transconductance also take in account on simulating the ultra thin fully depleted SOIMOSFET.