Device Processing Research Articles

Formation of Source/Drain Structures Using Nanosecond Laser Annealing for Multichannel GAA Mosfet Devices

As metal-oxide-semiconductor field-effect transistors (MOSFETs) devices approach their dimensional scaling limits, 3D structures such as gate-all-around FETs (GAAFETs) have been introduced to improve the electrical characteristics of transistors by increasing the effective channel width. In modern logic devices with a GAA structure, in-situ doped epitaxial silicon is grown on recessed source/drain (S/D) regions using selective epitaxial growth (SEG) process. However, the SEG process poses a competitive disadvantage in terms of complexity and cost. To simplify the integration process, we propose a method for forming S/D without relying on SEG. In this study, we investigate the formation of S/D using nanosecond laser annealing process in devices with multilayer channels. Three pairs of Si/Si0.7Ge0.3 multilayer films were deposited on Si (100) substrates using ultra-high vacuum chemical vapor deposition (UHVCVD). After deposition, boron and phosphorus dopants were implanted into the structure. Samples were then subjected to nanosecond laser annealing under various conditions using a krypton fluoride (KrF) pulse laser. Finally, we obtained recrystallized and doped films that function as S/D. Transmission electron microscopy (TEM) confirmed the microstructure of recrystallized films as function of increasing laser power density. Additionally, the dopant distribution was analyzed using secondary ion mass spectrometry (SIMS). High resolution X-ray diffraction (HR-XRD) was employed to examine the strain behavior in the films. Results indicate that the nanosecond laser annealing process is a viable method for forming S/D in devices with Si/SiGe multilayer channels. Acknowledgements This work was supported by the Joint Program for Samsung Electronics at Yonsei University and the Technology Innovation Program (20010598) funded by the Ministry of Trade, Industry & Energy (MOTIE).

Reservoir Computing with Graphene-Based Lithium-Ion Operated Electric Double Layer Transistors

In recent years, the rapid development of AI technology has faced serious problems such as increasing power consumption and computational costs, while the demand for AI technology has increased. One of the possible solutions to these problems is physical reservoir computing (PRC), a form of physical implementation of machine learning that is suitable for efficiently processing time series data. It utilizes nonlinear dynamics of physical phenomena in materials or devices for information processing. There is a potential for low power consumption and miniaturization. Therefore, PRC is promising for applications such as edge AI, which requires in-situ learning without transmitting to the cloud, in environments with limited computational resources. In this context, PRC has been studied using various physical phenomena such as optical response and magnetic spin, but its performance needs to be improved. Previously, our team developed ion-gating reservoirs (IGRs) using solid-state ionic materials, such as electric double layer (EDL) and redox-based transistors (PRC devices).[1,2] In particular, a hydrogen-terminated diamond-based IGR operating in an EDL mechanism has achieved high PRC performance by the nonlinear drain (I D) current response, although the performance needs to be further improved for practical use.[1] Since the nonlinear response of IGR originates largely from the I D -V G (gate voltage) characteristic of the transistor, choosing the channel semiconductor with unique electronic transport properties can give IGRs with different characteristics. In this viewpoint, we considered using semiconductors with ambipolar electron transport (n-type and p-type) in the transistor channel to improve the performance. Therefore, in the present study, EDL ambipolar transistors were fabricated using monolayer graphene as the channel semiconductor, which exhibits ambipolar conduction due to its electronic structure (Dirac cone). We investigated the fundamental electrical characteristics of the transistor and the PRC performance. This study used monolayer graphene deposited by chemical vapor deposition as the channel semiconductor with Au/Cr source and drain electrodes. Then, an electric double layer transistor (EDLT) was fabricated by depositing a Li+- conducting solid electrolyte (amorphous Li-Nb-O) and a gate electrode (LiCoO2) by pulsed laser deposition, as shown in Fig.(a). Applying various V G to the gate electrode causes Li+ transport inside the electrolyte. The formation of EDL at the graphene channel/electrolyte interface changes the electron carrier density in graphene. The I D through the channel can thus be controlled. We evaluated the electrical characteristics of this transistor and its performance as a PRC device through a benchmark task. The I D-V G characteristics measured by sweeping the V G from -1.5 V to +1.5 V are shown in Fig. (b). When a negative V G is increased (e.g., V G < -0.2 V), Li+ moves toward the gate electrode, and holes are injected into the channel surface, forming an electric double layer (p-type conduction). On the other hand, increasing a positive V G (e.g., V G>-0.2 V) injects electrons into the channel surface (n-type conduction). Therefore, V-shaped ambipolar transistor characteristics were clearly observed. The performance of this EDLT was evaluated by the 2nd-order nonlinear autoregressive moving average (NARMA2) task, which is a time-series data prediction task requiring nonlinearity and short-term memory and is thus widely used as a typical benchmark task of PRC. The performance is evaluated by the value of the normalized mean square error (NMSE) with the nonlinear transform output of the PRC and the target (i.e., a low NMSE means high performance). The predicted waveform by the EDLT reproduced the characteristics of the target waveform well, indicating that it predicted the time-series data with high accuracy. The NMSE (the test phase) was 0.015, which was notably lowered by 40% compared to the high-performance diamond-EDLT (NMSE: 0.020 in the test phase) [1] The high performance is attributed to the unique I D-V G and transient characteristic of the ambipolar EDLT. This work was supported by JST PRESTO (grant number, JPMJPR23H4).[1] D. Nishioka, et al., Sci. Adv. 8, eade1156(2022) [2] T. Wada et al., Adv. Intell. Syst. 5, 2300123(2023). Figure 1

Implementation of Integrate-and-Fire (IF) Characteristics of 1T-Neuron Induced Solely by Light Stimuli

With the exponential growth of global data processing demands, the concurrent slowdown in processing speed has become apparent. As a remedy, research endeavors in neuromorphic systems, emulating the structural and functional dynamics of the human brain, are actively underway. Neuromorphic systems research is classified into two distinct domains, wherein synapse investigation and neuron exploration are pursued independently. As with our previous studies[1], synaptic studies have witnessed advancements across diverse realms including materials, structures, and properties[2], but neuronal investigations have lagged considerably behind synaptic endeavors. This disparity primarily arises from the formidable challenges associated with replicating the intricate characteristics inherent to human neurons. To date, the majority of scrutinized neuron components have embraced a two-terminal configuration, renowned for its structural simplicity. Nevertheless, it has been beset by technical challenges on repeatability and reliability[3, 4]. The initial research stage on three-terminal neuron devices focused on Si-based transistors, which possess a complex structure since silicon itself cannot perform the neuron function, resulting in significantly increased power consumption, disadvantageous in light of the semiconductor trend toward miniaturization.[5]. In contrast to prior investigations, this study endeavors to employ titanium dioxide (TiO2), an oxide semiconductor, as the channel material, and seeks to realize integrate-and-fire (IF) characteristics utilizing a simple 1-transistor (1T) structure with a dual gate dielectric, one of which induces abrupt changes in conductivity in the transfer curve by supplying charges and capturing them at the interface of channel layer and dielectrics. Utilizing a 1T configuration obviates the need for intricate circuitry, thereby yielding reduced power consumption. Furthermore, the most significant feature of this study is the successful implementation of IF characteristics induced solely through light stimulation without electrical stimuli, unprecedented in previous reports. While conventional neuron components primarily exhibit firing characteristics induced by electrical stimuli, with certain investigations extending to modulation through the addition of light[6], our research uniquely simulates the emergence of IF properties exclusively via optical stimulation, devoid of any voltage input. The feasibility of such photo-induced firing is attributed to the outstanding photoresponsivity of TiO2 material and its capacity to control the lifetime of the device under 365 nm wavelength light stimulation. Hence, our study represents a significant advancement in the research phase devoted to mimicking human neuronal characteristics. It holds promise for emulating a broader spectrum of human brain activities, particularly regarding low-power consumption. As a result, we anticipate an enhanced capacity to replicate sensory perceptions, including visual stimuli. Acknowledgments This work was supported by an Electronics and Telecommunications Research Institute (ETRI) grant funded by the Korean government [24ZB1330] and UST Young Scientist+ Research Program 2023 through the University of Science and Technology [23AB2710]. References Lee, J. and J.W. Lim, Replicating the Bright-Light Therapy of Seasonal Affective Disorder Using Dual-Gate Dielectric Synaptic Transistors: An Exploration of Neuromorphic Computing Approaches. ACS Applied Electronic Materials, 2024. 6(3): p. 1904-1911. Dai, S., et al., Recent Advances in Transistor ‐Based Artificial Synapses. Advanced Functional Materials, 2019. 29(42). Zhang, X., et al., An Artificial Neuron Based on a Threshold Switching Memristor. IEEE Electron Device Letters, 2018. 39(2): p. 308-311. Park, S.O., et al., Experimental demonstration of highly reliable dynamic memristor for artificial neuron and neuromorphic computing. Nat Commun, 2022. 13(1): p. 2888. Han, J.K., et al., A Review of Artificial Spiking Neuron Devices for Neural Processing and Sensing. Advanced Functional Materials, 2022. 32(33). Han, J.K., et al., Bioinspired Photoresponsive Single Transistor Neuron for a Neuromorphic Visual System. Nano Lett, 2020. 20(12): p. 8781-8788. Figure 1

Electrochemical Impedance Spectroscopy of Bi-Based Cathode for Pellet-Type All Solid-State Fluoride Shuttle Battery

All solid-state fluoride shuttle battery (ASS-FSB) is one of the most promising rechargeable batteries due to its high energy density and cost effectiveness. The FSB operates based on conversion reactions with multi-electron transfers and does not require the use of high-cost metals like those used in lithium-ion batteries (LIBs). Therefore, the ASS-FSB is expanding research field for next generation batteries. Electrochemical impedance spectroscopy (EIS) is widely used for the analysis of energy devices such as LIB electrodes, as it can divide complicated electrochemical reactions into elemental processes based on their characteristic time constants without the need to disassemble batteries. We have reported that 3D structured electrodes can be analyzed by optimizing equivalent circuits 1–3. Although EIS is a powerful tool to understand electrochemical elemental processes in energy devices, detailed EIS analysis of ASS-FSB has not been reported. Here, we investigate the EIS analysis of a pellet-type ASS-FSB composed of a Bi-based cathode and a PbSnF4 anode, using it as an example of ASS-FSB.A Bi-based cathode cell for EIS is composed of Bi cathode (Bi/ Ce0.95Sr0.05F2.95/AB = 25/70/5 by weight), Pb0.58Sn0.42F2 anode (Pb0.58Sn0.42F2/AB = 70/5 by weight) and Ce0.95Sr0.05F2.95solid electrolyte. The loading amount of the Bi-based cathode was 10, 20, 30 mg and that of the Pb0.58Sn0.42F2 anode was fixed to be 20 mg. A three-layer pellet cell (φ10 mm) was prepared in Ar atmosphere by applying a pressure stepwise and finally reaching 740 MPa. The cell was held with 4 bolts, followed by keeping the cell under vacuum. Prior to conducting the EIS, the cells were charge with a CC (120 µA)-CV (cut off voltage of 0.9 V, down to 40 µA) mode. The EIS was carried out after 1st charge with a frequency range from 1 MHz to 100 mHz at SoC of 100% and 140 ℃.Figure 1 shows the charge and discharge curves of the pellet-type ASS-FSBs with different cathode amount measured at 140 ℃. The discharge capacity of the ASS-FSBs with 10, 20, 30 mg cathode loading was 323, 359, and 359 mAh/g-Bi, respectively. The discharge capacity was 84%, 93%, and 93% against the theoretical capacity of Bi, confirming that ASS-FSBs, especially those for 20 and 30 mg, were fabricated properly. Figure 2 represents Nyquist plots of pellet-type ASS-FSBs with different cathode amount measured at SoC 100% and 140℃. The Nyquist plots clearly show one semicircle in high-frequency region (see Fig.2 right) and a line with an angle of ~45゜ in middle-frequency region (see Fig.2 right) and a line with an angle of higher than 45゜ in low-frequency region (see Fig.2 left). Although the loading amount of the Bi cathode are different, the diameter of the semicircles is almost same, indicating that the semicircle is derived from a common element among the pellet-type ASS-FSBs. The length of the line with an angle of higher than 45゜ decreased with increase of the loading amount of the Bi cathode. The decrease is due to the increase of limiting capacitance 2. Meanwhile, the line with an angle of ~45゜ is characteristic feature of an ion transport property in depth direction. In addition, the length of the line increased proportionally to the loading amount of the Bi cathode, supporting that the line is derived from the reaction distribution. The results indicate necessity to adopt a transmission line model to analyze the pellet-type ASS-FSB by EIS.In the presentation, equivalent circuit design using a transmission line model and its attribution for the pellet-type ASSFSB with Bi-based cathode will be discussed with EIS data measured with various condition on SoC and temperature. References H. Nara, D. Mukoyama, T. Yokoshima, T. Momma, and T. Osaka, J. Electrochem. Soc., 163, A434–A441 (2016). H. Nara, K. Morita, D. Mukoyama, T. Yokoshima, T. Momma, and T. Osaka, Electrochim. Acta, 241, 323–330 (2017). H. Nara, D. Mukoyama, R. Shimizu, T. Momma, and T. Osaka, J. Power Sources, 409, 139–147 (2019). Acknowledgement This presentation is based on results obtained from a project, JPNP21006, commissioned by the New Energy and Industrial Technology Development Organization (NEDO). Figure 1

(Invited) Tunneling Phenomena and Ohmic Contact Formation at Non-Alloyed Metal/Heavily-Doped SiC Interfaces

To clarify the formation mechanism of alloyed ohmic contacts on SiC by high-temperature sintering (~1000°C) and to improve the fabrication process of SiC electronic devices, a physical understanding of fundamental properties at non-sintered (non-alloyed) metal/heavily-doped SiC interfaces is indispensable. This paper reviews tunneling phenomena through a thin Schottky barrier at non-alloyed contacts on heavily-doped SiC, and design guidelines toward low-resistance ohmic contacts are proposed based on transport modeling.The first target was a Schottky contact formed on a heavily nitrogen-doped n-type SiC epitaxial layer. Vertical Schottky barrier diode (SBD) structures were fabricated by systematically varying the donor density in the epitaxial layers (up to 1019 cm−3), and the current-voltage (I-V) characteristics were analyzed based on a numerical calculation of direct tunneling (DT) current, in which energy integration of carrier distribution and tunneling probability is performed. Note that the DT transport describes both the thermionic field emission (TFE) and field emission (FE). The numerical calculation reproduces well the experimental I-V curves for vast ranges of the donor density, barrier height, and applied voltage. The authors also formed Schottky contacts on heavily aluminum-doped p-type SiC epitaxial layers and revealed unique DT transport associated with the complicated valence band structure of SiC. The valence band in SiC has a split-off band with a light effective mass (m * = 0.2m 0), which is located at the energy of several tens of meV above the topmost heavy- and light-hole bands (m * = 1.6m 0). Reflecting the exponential contribution of the effective mass to the tunneling probability, carrier transport through non-alloyed contacts on heavily-doped p-type epitaxial layers is dominated by hole tunneling through the split-off band.The next step was to clarify how different the interface properties are between the cases of epitaxial and ion-implanted layers. It was found that vertical SBDs fabricated with heavily phosphorus- and aluminum-implanted n- and p-type SiC, respectively, both exhibit several orders of magnitude larger current than those with epitaxial layers having almost identical doping densities. Systematic analysis of the Schottky barrier height through capacitance-voltage (C-V) measurement revealed that there is no significant difference in the barrier height at the contacts on ion-implanted and epitaxial layers, indicating a contribution of a carrier transport process other than DT. The enhanced current is likely explained by trap-assisted tunneling (TAT) through implantation-induced deep levels.Toward modeling of contact resistivity based on the deep understanding of the tunneling phenomena (DT and TAT) gained above, experimental characterization and numerical analysis of the contact resistivity at non-alloyed ohmic contacts formed on heavily ion-implanted n- and p-type SiC were performed. At non-sintered Mg and Ti contacts on n-type SiC (donor density: 2×1020 cm−3), corresponding to the barrier height of 0.7 and 1.0 eV, respectively, an extremely low contact resistivity of 1-2×10−7 Ωcm2 was achieved without performing any thermal treatment after the electrode formation. As for p-type SiC with the acceptor density of about 1×1020 cm−3, a Ni contact (barrier height: 1.7 eV) exhibited a relatively low contact resistivity of 9.8×10−3 Ωcm2 without sintering. Through comparison between the contact resistivities experimentally and numerically obtained, how the dominant tunneling process changes depending on the doping density is carefully discussed, and a physics-based model considering the contributions of DT and TAT to predict the contact resistivity at non-alloyed ohmic contacts on implanted SiC is proposed as follows: the contact resistivity is significantly reduced thanks to a contribution of the TAT when the doping density is below about 1020 cm−3, and the contact resistivity at further high doping density sharply decreases and is well predictable based on the DT theory. The proposed model provided several quantitative guidelines regarding the doping density and barrier height for designing low-resistance ohmic contacts on SiC.The model to predict the contact resistivity standing on the physics of tunneling is beneficial not only for a deeper understanding of the ohmic contact formation on SiC but also for exploring a novel low-temperature fabrication process toward low-resistance ohmic contacts. Besides, the high-field tunneling phenomena revealed in this study are expected to be commonly observed at contacts formed on other wide-bandgap semiconductors. Thus, the present data and model can also give a critical insight into the ohmic contact formation on these materials.

Physicochemical Impedance Modelling of Porous Electrodes in All-Solid-State Electrochemical Devices

Fundamental knowledge about performance limiting processes in electrochemical devices like battery-, fuel- and electrolyzer-cells is mandatory for a model-aided development. The method of choice to analyze these processes is electrochemical impedance spectroscopy, enabling a separation of electrochemical processes differing in their relaxation frequencies. In order to improve the deconvolution of these processes in the impedance spectrum, the distribution of relaxation times (DRT) analysis is a well-established method [1].In case of porous, multiphase electrodes, the DRT usually doesn’t enable a simple correlation of a peak in the DRT with a single polarization process in an electrode. The complex coupling of electronic and ionic charge transport via charge transfer reactions, often described by a transmission line model (TLM) [2-4], induces a number of peaks in the DRT. TLM parametrization just by operating and/or electrode parameter variations is often insufficient. Since different parameter sets can result in identical spectra [3], a straightforward CNLS-fit is insufficient and a pre-parameterization by determining at least a few model parameters independently is required.In this study, impedance spectra of two all-solid-state electrochemical devices, an all-solid-state battery and a solid oxide cell, are analyzed by the distribution of relaxation times. Physicochemically motivated impedance models based on the TLM-approach were derived, pre-parameterized and applied to quantify different loss processes in the cells. The pre-parameterization included microstructural parameters obtained by focus ion beam tomography and conductivity data. The model development and areas of application will be discussed in detail within this contribution, focusing on the differences between the two investigated all-solid-state electrochemical devices.

Bay-Region, Nitrogen Functionalized Perylene Diimides for Printed Electronic Sensors

The chemistry of organic conjugated materials is rich. Chemical structures can be infinity tuned to tailor optical, electronic, and physical properties. With an ability to transport electrical charge, such materials have found widespread use in electronic devices ranging from solar cells to sensors, so called ‘organic electronics. As organic electronic technologies move towards commercialization there becomes a focus on cost and sustainably. Perylene diimide (PDI) is a classic organic dye that has been well manipulated and studied in organic electronics and championed as chemically versatile, high-performance, and accessible (i.e. low-cost). While many electronic devices featuring PDI as an active electronic component have been engineered to achieved high performance, sustainably (i.e. greenness) has often been overlooked. Our research team at the university of Calgary is a member of the Canadian NSERC Green Electronics Network (GreEN) developing new materials and processes for sustainable organic electronic devices. This presentation will showcase two new PDI dyes, modified with active pyrrole or amine functional groups to produce electronically active, large area, green solvent roll-coated films. The materials design, chemistry, properties, and utility as electronic amine sensors, fully roll coated, will be discussed.

Microwave-Induced Crystal Growth of Metal Halide Perovskites to Enhance the Photovoltaic Performance

This poster presents a novel approach for the growth of perovskite crystals utilizing microwave irradiation, offering distince advantages over the conventaional thermal annealing. This approach effectively mitigates both surface and bulk defects, which consequently enhances the performance of perovskite solar cells. First, we demonstrate that microwave irradiation can sucessfully crystallize the nickel oxide (NiOx) thin films at low processing temperatures and substantially reduced processing times, High electrocal conductivity and transmittance are realized comparable to conventionally annealed NiOx films. Morevoer, the microwave-annealed NiOx films exhibit distinct features of chemical compositions with less Ni>3+ attributed to In and Sn cations unexpectedly diffused from the underlying ITO layer. Additionally, we show a new strategy for the perovskite crystal growths that combines microwave irradiation with simultaneous defect passivation with trioctyl-n-phosphine oxide (TOPO). This approach leads to the growth of perovskite crystals with coordinated TOPO ligands within the film, resulting in suppressed non-radiative recombination, reduced defects, and improved morphology compared to conventionally annealed perovskites. The combined effects of enhanced conductivity in MWA-NiOx and defect passivation in perovskite films contribute to the enhanced performance of solar cells, suggesting promising applications for microwave-assisted processing in optoelectronic devices.

(Invited) Interface Design Strategy for Solid State Batteries

Solid state battery technology shows the potential to be competitive to commercial Li ion batteries. This talk will focus on understanding the fundamental interface reaction and evolution of electrochemical processes in related battery materials and devices, and discuss the design opportunities for advanced solid state batteries. Specifically, unique electrochemical reaction related to constriction susceptibility at solid-solid interface will be discussed, understanding of which forms the opportunity to design solid state batteries with stable cycling at high current density and areal capacity.

Carbon-Based Perovskite Solar Cells: Interface Engineering of 5-AVAI Additive

Perovskite materials have great potential for high efficiencies in photovoltaic devices, with the best performances exceeding 26% in a single junction. We now need to further develop perovskite device architectures that combine ease of industrial development with effective durability. Among the alternatives, mesoporous frameworks based on metal oxide and carbon are promising due to their inherent high stability. In the presented work, two perovskite formulations will be compared: MAPbI3 and (5-AVA)xMA1-xPbI3. Both were infiltrated using drop casting as a final step, which provides a clean industrial process for large scale and stable perovskite devices. The aim was to highlight the differences in behavior between devices based on the traditional MAPbI3 perovskite when fabricated with or without 5-ammonium valeric acid iodide (5-AVAI) as an additive. A detailed study with a large series of characterizations (macroscopic functional properties, LBIC imaging, photoluminescence, UV-visible spectroscopy, X-ray diffraction, impedance spectroscopy) has provided new insights into how carbon-based mesoscopic perovskite solar cells perform and degrade.Perovskites based on AVAI possess higher performances and durability than the original perovskite formulation, however they also demonstrated a higher potential for species diffusion and interface contamination. A special attention will be thus given to the method used to measure performances by analyzing J-V curves at different scan rates. Indeed, this allowed us to define boundary conditions allowing the observation of two different states within our devices (defined as ‘stable’ and ‘metastable’). This behavior was interpreted as a structural transition [1] and can vary according to the perovskite formulation. In addition, the degradation of performance with aging time under damp-heat conditions was found related to a different mechanism in devices formulated with or without AVAI: the critical damage occurring either at the perovskite interfaces or within the perovskite itself.

Polycrystalline inclusion-free growth of thick, lattice-matched SiGeC with high substitutional Carbon concentrations up to 2%

State of the art semiconductor manufacturing seeks to expand its range of Si-based materials with novel properties, boosting performance to comply with customer demands. These materials mostly comprise of large lattice parameter materials like Ge-rich or group III/V alloys. To reduce costs, heteroepitaxy of these materials on Si substrates is desired. Buffer solutions like SiGe [1] or Ge Virtual Substrates [2] or III/V patterned Superlattices [3] usually do not result in threading dislocations densities below 106 cm-2, which affects device performance and process robustness.The incorporation of Carbon into SiGe allows to tailor SiGe’s lattice parameter, theoretically enabling to match the Si substrate’s lattice parameter. This allows the strain-free growth of a few hundred nanometers up to several micrometers thick SiGeC on a Si substrate without the formation of dislocations.The growth of SiGeC was performed in a 300 mm industrial standard Reduced Pressure-Chemical Vapor Deposition (RP-CVD) reactor. Si2H6, GeH4 and SiH3CH3 were used as precursors with constant flows at 550°C, 10 Torr. Interstitial (C Int) and substitutional Carbon (C Sub) concentrations were determined by XPS. [4]For a 50 nm SiGeC layer with C Int~0.4% and C Sub=2.0%, smooth surfaces were observed by top view Scanning Electron Microscopy (SEM) (Fig. 1 (a)) and confirmed by Atomic Force Microscopy (AFM) (Fig. 1 (b)) with a RMS of 0.23 nm. X-Ray Diffraction measurements showed the growth of SiGeC lattice matched to the Si substrate (Fig. 1 (c)). Above ~250 nm, islands are visible on the surface by top-view SEM (Fig. 2 (a)) with the island’s diameter increasing as the SiGeC layer thickness increased. Transmission Electron Microscopy showed a dislocation free growth and that the islands/clusters were polycrystalline, originating from several hundred nanometers below the surface (Fig. 2 (b)).Growing SiGeC of the same thickness range under the same growth conditions with lower SiH3CH3 flow, resulted in fully substitutional incorporated Carbon with C Sub~1.0% and C Int below the detection limit. No islands/clusters were observed by SEM and AFM (Fig. 2 (c)). The elimination of C Int allowed to suppress the formation of polycrystalline SiGeC inclusions. The starting point of these defects should be due to point defects formed by C int clusters.Even if the reduction of SiH3CH3 flow resulted in defect free growth of thick SiGeC on Si substrates, other approaches are mandatory to incorporate higher C Sub into the SiGeC layer to achieve the desired novel properties. Dhayalan et al. [5] showed in the literature the growth of SiC with 2% of Carbon (C Sub=1.6%) without the formation of islands/clusters by introducing HCl during a Cylic Deposition Etch (CDE) process. These results are based on the preferential etching of C int point defects, which are preferentially etched by HCl, reducing the amount of C Int and preventing the formation of islands/clusters. Meanwhile, the C Sub was not significantly affected by HCl etching.The impact of HCl on the growth of SiGeC was evaluated by performing co-flow (simultaneous growth and etching) and CDE (separate growth and etching steps) with various small HCl flows, preventing aggressive etching of monocrystalline SiGeC, and varying the duration of the CDE etch step. The introduction of HCl during a co-flow process changed the C and Ge incorporation. The C Sub concentration varied between 2.0% and 1.9% (Tab. 1), while the interstitial Carbon concentration varied between 0.7% and 0.3%, which is the lower detection limit of the XPS measurement. The Germanium concentration increased from 20% to 25% (Tab. 1). The growth of SiGeC without Chlorine showed the transition to a polycrystalline material at the same Carbon composition for higher Ge concentrations. XRD profiles (Fig. 3) showed a good crystalline quality, well-defined SiGeC peak, outlining a reduction of C Int thanks to the HCl etching. The CDE process did not result in significant compositional changes. To gain further understanding a wider range of HCl flows and thicker layers will be investigated in the future.The growth of dislocation free, high crystalline quality SiGeC with high C Sub was demonstrated. It was outlined that interstitial Carbon was likely to create point defects which lead to polycrystalline islands/cluster formation for thick films. HCl was shown to reduce interstitial Carbon incorporation. Other materials with large lattice parameters could benefit from the knowledge gained on defect reduction and lattice matched growth.[1] Y. Bogumilowicz et al., J. Cryst. Growth, vol. 283, no. 3, 2005.[2] J. M. Hartmann, J. Cryst. Growth, 2018.[3] J.-S. Park, M. Tang, S. Chen, and H. Liu, Crystals, vol. 10, no. 12, 2020.[4] J. Vives, J Mater Chem C, 2023.[5] S. K. Dhayalan et al., ECS J3ST, p. 6, 2017. Figure 1

(Invited) Improvement of Surface Morphology of Vicinal Off Angled 4H-SiC Epitaxial Wafer for GaN/SiC Hybrid Devices

Wide gap semiconductor materials like SiC, GaN, and Ga2O3 are well-known as one of key technologies for realizing carbon neutrality. Indeed, SiC devices are used in many applications including electric vehicles, train systems, and consumer products. AlGaN/GaN HEMT devices also used in low voltage power source like AC adopters and 5G telecommunication systems. However, both devices have still improved issues. For SiC devices, the performance of MOS interface at the gate structure is still a big issue. On the other hand, GaN has superior performance of MOS interface and HEMT structure on the gate area. However, device processing reliability of GaN is worse compared with SiC, especially ion implantation process. So that, GaN is difficult to control avalanche characteristics compared with SiC. To solve this problem, GaN/SiC hybrid devices have been proposed [1]. In this device, a drift layer is constructed by 4H-SiC epilayer and a gate is constructed by GaN HEMT structure. By applying this structure, both superior performance of AlGaN/GaN HEMT at the gate area and controllability of avalanche characteristics of 4H-SiC drift layer can be realized. To realize this hybrid devices, AlGaN/GaN HEMT structure should be hetero epitaxially grown on 4H-SiC epilayer. This hetero epitaxial growth is a big issue on this study. As well known, the off angle of 4H-SiC substrate for GaN hetero epitaxy and 4H-SiC homo epitaxy is a quite different. The off angle for GaN is less than 0.5 degree and that for 4H-SiC is 4 degree. In our past study, we demonstrated that 4H-SiC layer could be grown on 0.75 degree off 4H-SiC Si-face substrate [2]. But this past result is not enough to grow GaN epilayers on such off angled 4H-SiC epitaxial wafers. By reducing wafer off angle less than 0.75 degree, large macro step bunching and other polytype was generated on 4H-SiC epitaxial wafer surface, and it is difficult to grow GaN layers on such 4H-SiC epitaxial wafers.In this study, we try to improve the surface morphology of 4H-SiC Si-face epitaxial wafer with off angle less than 0.5. To do this purpose, we have focused on an in-situ H2 etching process to suppress the generation of large step bunching on the grown 4H-SiC epitaxial layer surface. This in-situ H2 etching process is well known to make a risk to generate the step bunching on the 4H-SiC surface [3]. In addition, we confirmed the quality of the grown 4H-SiC epilayer by hetero epitaxially growing AlGaN/GaN HEMT layer on that grown 4H-SiC epilayer. As the result, we could obtain 4H-SiC epitaxial layer with supeclor surface morphology on 0.5 degree off 4H-SiC Si-face substrate by suppressing the in-situ H2 etching process before the growth process. From an AFM measurement, RMS values of grown 6 μm thick epitaxial layer surface are improved from about 2 nm to 0.2 nm by suppressing the in-situ H2 etching process before the growth process (Fig. 1). This value is the same as the 4H-SiC epitaxial layer grown on 4 degree off angled substrate. We also confiermed that othe polytypes were not included in grown epilayer by photoluminescenss imaging mesurement. The quality of the grown epilayer was also investigated by I-V charcterisics of Ni/4H-SiC SBD fablicated on grown epilayer surface. The blocking voltage about 600V and low n value of 1.02 were obtained as the yield of 80 % (N=10).We also hetero epitaxially grew AlGaN/GaN HEMT structures on grown 6 μm thick 4H-SiC epitaxial layer with 0.5 degree off angle. As the result, RMS values of 0.8 nm was obtained as the surface roughness of AlGaN layer which was the top layer of grown AlGaN/GaN HEMT structure. This value is the same as that layer grown on on-axis 4H-SiC substrate. We also investigated Vth dispersion from C-V measurement of capacitors fabricated on AlGaN layer of AlGaN/GaN HEMT structure. By reducing wafer off angle of 4H-SiC substrate from 4 to 0.5 degree, this dispersion was improved from ±0.98V to ±0.32VThese results indicated that GaN layers with good surface morphology and high quality 4H-SiC homoepitaxial layer can be taken balance by using 0.5 off axis 4H-SiC substrate and the realization of GaN/SiC hybrid devices can be expected.[1] J. W. H. Jiang, Q. Jiang, and K. J. Chen, IEEE Trans. Electron Devices 63, 2469 (2016).[2] K. Kojima, K. Masumoto, S. Ito, A. Nagata, and H. Okumura, ECS transaction 58, 111 (2013).[3] K. Kojima, S. Kuroda, H. Okumura, and K. Arai, Mater. Sci. Forum 556-557, 85 (2007). Figure 1

(Invited) Boron δ-Doping and Silicon Epitaxy on Chlorinated Silicon Surfaces

The halogen-silicon system has been well-studied over the years due to the prevalent use of halogen-based plasmas for silicon device processing and for its role in fostering chemical reactions leading to the functionalization of silicon surfaces. Most recently, our work has demonstrated the effectiveness of a single monatomic layer of chlorine to resist the adsorption of chlorinated molecular dopant precursor gases and support the epitaxial growth of silicon from a molecular beam source. We have leveraged these findings to realize atomic-scale quantum devices in which we are able to confine dopant atoms to atomically-precise regions of a nominal single plane of silicon with sufficient density to support ohmic conduction across these structures at mK temperatures. Here, I will discuss our process of using BCl3 to obtain single layers of heavily boron-doped silicon with an extremely high active carrier concentration (> 1014 cm-2), as well as the role of the chlorinated silicon surface in supporting the growth of high quality, epitaxial silicon capping layers.

(Invited) Advances in Oxide Thin-Film Transistor Based Inverter Technology

Several advantages in oxide device processing, including low-temperature processability and exceptional uniformity on a large scale, render oxide device technology essential for a wide range of next-generation electronics. Advancing oxide thin-film transistor-based circuits marks a crucial milestone in developing the next generation of cost-effective ubiquitous electronics. This moves forward oxide-TFT to the forefront of transistor technology, marking the commencement of a new era characterized by low-cost mass-production and high-performance. Extensive efforts have been devoted to developing oxide inverters, including NMOS, and CMOS inverters, and excellent characteristics, such as high-speed separation, low-power dissipation, and sufficient noise marge, have been already demonstrated. Nevertheless, persistent open issues, such as the absence of high-performance p-channel oxide-TFT and the lack of doping control, in oxide semiconductors impede the progress of oxide inverter technology development to the next levels. This presentation reviews recent advances in oxide-TFT inverter technology and delves into open issues that should be addressed for oxide-TFT-based circuit applications. First, I will present the advancements in oxide-TFT inverter technology, encompassing NMOS, PMOS, and CMOS, primarily drawing from our research activities. Subsequently, we will elucidate and discuss strategies for addressing open issues for the development of high-performance oxide-TFT-based circuit applications.

(Invited) Group IV Mid-Infrared Optoelectronics Leveraging Nanoscale Growth Substrates

Mid-infrared (MIR) optoelectronic devices are of utmost importance to a plethora of applications such as night vision, thermal sensing, autonomous vehicles, free-space communication, and spectroscopy. To this end, leveraging the ubiquitous silicon-based processing has emerged as a powerful strategy that can be accomplished through the use of group IV germanium-tin (GeSn) alloys. Indeed, due to their compatibility with silicon and their tunable bandgap energy covering the entire MWIR range, GeSn semiconductors are frontrunner platforms for compact and scalable MIR technologies. However, the GeSn large lattice parameter has been a major hurdle limiting the quality of GeSn epitaxy on silicon wafers. These limitations are further exacerbated as Ge1−xSnx layers and heterostructures with Sn contents at least one order of magnitude higher than the solubility are needed for device structures relevant to MWIR applications. In this regime, the as-grown layers are typically under a significant compressive strain, which impacts the bandgap directness and increases its energy at the Γ point, thus hindering the device performance and limiting the covered range of the MIR spectrum. This compressive strain build-up not only affects the band structure but also limits the incorporation of Sn atoms in the growing layer, making the control of Sn content a daunting task.In this presentation, we will show and discuss how sub-20 nm Ge nanowires provide effective compliant substrates to grow Ge1−xSnx alloys with a composition uniformity over several micrometers with a very limited build-up of the compressive strain. Ge/Ge1−xSnx structures with Sn content spanning the 6 to 18 at.% range are achieved. We will also demonstrate the integration of the obtained materials in optoelectronic device processing leading to tunable detectors and emitters [1,2]. For instance, photodetectors based on these materials were found to exhibit a high signal-to-noise ratio at room temperature and provide a tunable cutoff wavelength covering the 2.0 µm to 3.9 µm range. Additionally, the processed detectors were also integrated in uncooled imagers enabling the acquisition of high-quality images under both broadband and laser illuminations without the use of the lock-in amplifier technique. Finally, progress towards achieving nanoscale GeSn lasers will also be discussed [2].

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Introduction Miniaturization of field-effect transistors (FETs) have serious issues in enhanced leakage current, short-channel effect, and power consumption. In this regard, the vertical gate all-around (VGAA) structure using the III-V compound semiconductor nanowires (NWs) is expected as alternative transistor to solve the problems in leakage current and short channel effect. There is still challenge in decreasing power consumption of the FET because the reduction in subthreshold slope (SS) has physical limitation in thermionic carrier transport (SS = 60 mV/dec). Tunnel FETs (TFETs) can lower the SS less than the physical limitation in MOSFETs and are expected to be used as next-generation low-voltage switching devices. We have demonstrated vertical gate-all-around (VGAA) TFET using III-V/Si tunnel junction which was formed by the selective-area growth of III-V NWs on Si and achieved a steep SS characteristics and complementary operation [1]. These demonstrations should be expanded on silicon-on-insulator (SOI)(111) platforms toward circuit applications using the III-V/Si VGAA-TFETs. Here, selective-area growth of the InAs NWs on thin SOI(111) substrates and demonstrated InAs/Si VGAA-TFETs on SOI platforms.Experimental procedureFirst, a 35-nm-thick SiO2 film was formed on p-type SOI(111) by thermal oxidation. The SOI thickness was 600 nm. Periodical circular openings were formed using electron beam lithography and dry/wet etchings. Next, InAs NWs were grown by selective-area growth. Here, we used a pulse growth technique to orient NWs in the vertical <111>B direction on a nonpolar SOI substrate, making the substrate surface polar (111)B, and aligning vertical NWs [2]. Next, we fabricated VGAA-TFETs by using three-dimensional device process in previous reports [1]. First, Hf0.8Al0.2O were formed as gate oxides by atomic layer deposition (ALD). Next, 200 nm-thick tungsten (W) was deposited around the NW sidewalls as gate metal. After that source metal (Ti/Au) was evaporated 20 nm/50 nm on the substrate by EB vapor deposition. Next, benzocyclobutene (BCB) was used as isolation layer between gate and drain metals. Then drain metal (Ti/Pd/Au) was evaporated 20 nm/20 nm/50nm on the top of the NWs. Finally, the VGAA-TFETs were annealed at 350 - 400°C in order in N2 for ohmic contacts in the source and drain regions. VGAA-TFETs were measured after annealing for each temperature.ResultsThe growth results showed vertical InAs NWs were successfully integrated on the p-SOI(111) substrates. The grown InAs NWs have hexagonal pillar structures surrounded with {-110} vertical facets and (111) B planes. Each NWs were composed of axial Zn-pulse doped intrinsic/Si-doped n-type/Sn-pulse doped n+-type NW segments. The average height is inversely proportional to the square of the diameter. Therefore, as similar to the conventional selective growth of InAs NWs on Si(111), the surface diffusion process of In atoms was dominant for the NW growth on SOI(111) surface.Transfer characteristics of the fabricated VGAA-TFET after annealed at 350°C indicated the tunnel current in the InAs/Si tunnel junction was electrically modulated by gate bias. The minimum SS was 37 mV/dec at VDS = 0.50 V, which was less than the theoretical limitation of conventional MOSFETs.The on-state current was 21 nA/μm at drain and source (VDS) of 1.00 V. The off current was 6.5 fA/μm when VDS was 1.00 V. Also, the threshold voltage (VTH) was 0.55 V. Transconductance was 31 nS/μm at VDS = 0.50 V. The measured current and transconductance were normalized by the number of NWs and the gate outer perimeter.We also investigated anneal temperature dependence of the device performance. The increasing in anneal temperature slightly lowered the minimum SS from 37 mV/dec to 23 mV/dec. And the on-state current was increased with increasing the anneal temperature. However, nonlinearity in the output IDS – VDS curve was enhanced with increasing the anneal temperature. This was assumed to be formed Schottky contact on the source metal. At the higher anneal temperature above 380°C, Ti/Au source metal possibly formed silicide (TiSi2) layer at the Ti/p-SOI interface. Thus, the contact resistance was decreased by the silicidation, and the on-state current was increased. However, Schottky contact of Au/Si was partially formed through the silicidation layer due to the very thin Ti interlayer. One of the possible approaches was to increase the Ti thickness or to use Al or Cu as single layer film. Further improvement of the device performance will be discussed.[1] K.Tomioka et al., IEEE IEDM. Tech. Dig. (2020) 429-432[2] K.Tomioka et al., Nano Lett. 8(2008) 3475-3480

DrHouse: An LLM-empowered Diagnostic Reasoning System through Harnessing Outcomes from Sensor Data and Expert Knowledge

Large language models (LLMs) have the potential to transform digital healthcare, as evidenced by recent advances in LLM-based virtual doctors. However, current approaches rely on patient's subjective descriptions of symptoms, causing increased misdiagnosis. Recognizing the value of daily data from smart devices, we introduce a novel LLM-based multi-turn consultation virtual doctor system, DrHouse, which incorporates three significant contributions: 1) It utilizes sensor data from smart devices in the diagnosis process, enhancing accuracy and reliability. 2) DrHouse leverages continuously updating medical knowledge bases to ensure its model remains at diagnostic standard's forefront. 3) DrHouse introduces a novel diagnostic algorithm that concurrently evaluates potential diseases and their likelihood, facilitating more nuanced and informed medical assessments. Through multi-turn interactions, DrHouse determines the next steps, such as accessing daily data from smart devices or requesting in-lab tests, and progressively refines its diagnoses. Evaluations on three public datasets and our self-collected datasets show that DrHouse can achieve up to an 31.5% increase in diagnosis accuracy over the state-of-the-art baselines. The results of a 32-participant user study show that 75% medical experts and 91.7% test subjects are willing to use DrHouse.

Памяти Александра Степановича Бугаёва

Information is presented about the deceased Alexander Stepanovich Bugayov, DrSci Phys&amp;Math, professor, Corresponding Member of the Russian Academy of Sciences since 1994 in the Department of Computer Science, Computer Engineering and Automation, full member of the Russian Academy of Sciences since 2000 in the Department of Nanotechnology and Information Technology (Section of Computing, Location, Telecommunication Systems and Element Base), founder of the Department of Solid-state Electronics and Radiophysics of the Moscow Institute of Physics and Technology, Head of the Department of Vacuum Electronics and At the same time, he is the scientific director of the MIPT Center for Open Systems and High Technologies, Head of the Laboratory of Wave Electronics of the V.A. Kotelnikov Institute of Radio Engineering and Electronics of the Russian Academy of Sciences, Deputy Director of the State Research Institute of Electronic and Ion Optics, Chief Researcher of the Department of Scientific and Innovative Activities of the South Ural State University. Professor of the Computer Engineering Department of the Higher School of Economics, Professor of the St. Petersburg State University of Aerospace Instrumentation, an outstanding specialist in the field of condensed matter physics, semiconductor physics, acoustic and spin-wave electronics, computer science and mathematical modeling of semiconductor and solid-state information processing devices. The main biographical data are given: studies at the Moscow Institute of Physics and Technology (Faculty of Physical and Quantum Electronics), postgraduate studies and work at MIPT, defense of a PhD (physical and mathematical sciences) dissertation, authorship of more than 250 scientific papers in scientific journals, participation in Russian and international conferences and seminars, editorial work in scientific journals. Work as a member of the Presidium of the Russian Academy of Sciences, membership in various Russian and international scientific societies and expert councils.

Can the Ability to Play Steady Beats Be Indicative of Cognitive Aging? Using a Beat Processing Device.

This study aimed to examine whether different rhythm idioms significantly affect the reproduction accuracy of older adults and whether the participants' age and personal current engagement in music affect their ability to reproduce rhythm. A total of 79 older adults participated in the study. Participants were required to reproduce six different rhythm idioms, and their accuracy in rhythm reproduction was measured using the R index. The data were analyzed considering the participants' age sub-group and current engagement in music. The findings showed differences in reproduction accuracy across various rhythm idioms, particularly in relation to steady recurring notes and dotted notes with different intervals. The highest reproduction accuracy was found for the isochronous beat pattern, while the rhythm idiom starting with longer intervals yielded the lowest accuracy. Age and current personal engagement in music did not significantly affect rhythm performance. However, the study identified a significant correlation between decreased accuracy in reproducing a steady rhythm and diminished general cognitive ability. This study indicates that rhythm performance can be indicative of cognitive abilities related to temporal information processing. The findings support the potential use of rhythm tasks to evaluate cognitive performance in older adults with varying cognitive levels.

Augmented Reality as an Assistive Tool for Learning How to Use Medical Devices

In education, especially in medicine and medical technology, augmented reality (AR) is a promising innovation that can support and enrich the learning process. This technology offers the ability to present complex information on medical devices more interactively, enhance understanding, and provide a practical experience as an alternative to using real devices. AR can be integrated into the process of learning how to use medical devices. In particular, AR can improve information retention, facilitate understanding of technical concepts, and reduce errors when students use medical devices in simulations. It also allows students to practice in a safe environment before dealing with real situations. Despite its great potential, the application of AR in the learning process of medical devices also has several challenges. The need for infrastructure and compatibility is one barrier from a technological perspective. Meanwhile, from a pedagogical perspective, training for teachers to utilize AR effectively is essential. However, despite these challenges, with the right approach, AR has the potential to increase user engagement, deepen understandings of concepts, and enrich the learning experience. Also, with the development of technology and increasing affordability, we posit that these barriers will lessen over time. Keywords: AR, augmented reality, learning process, medical devices