Performance Of Various Devices Research Articles

Photovoltaic effect on the performance enhancement of organic light-emitting diodes with planar heterojunction architecture

Organic light-emitting diodes (OLEDs) with planar heterojunction (PHJ) architecture consisting of photovoltaic organic materials of fullerene carbon 60 (C60) and copper (II) phthalocyanine (CuPc) inserted between emitting unit and cathode were constructed, and the photovoltaic effect on OLEDs performance was studied. The electroluminescent (EL) characteristics and mechanism of device performance variation without and with different PHJs (herein including C60/CuPc, CuPc/C60 and CuPc) were systematically investigated in red, green and blue OLEDs. Of the three combinations, OLEDs with C60/CuPc showed the highest efficiency. It is revealed that the photovoltaic C60/CuPc PHJ can absorb part of photons, which are radiated from emission zone, then form excitons, and dissociated into free charges. Consequently, the high device efficiency of OLEDs performance improvement was acquired. This research demonstrates that PHJ consisting of two n- and p-type photovoltaic organic materials could be a promising methodology for high performance OLEDs.

Hybrid Perovskite Thin Films as Highly Efficient Luminescent Solar Concentrators

Organic–inorganic hybrid perovskite (PVSK) compounds are at the forefront of photovoltaic research, consistently surpassing silicon solar cells in power conversion efficiency. Possessing high refractive index, broad absorption spectrum, and superior quantum yields, hybrid PVSK thin films are theoretically also ideal candidates for luminescent solar concentrators (LSCs). In practice, however, the possibility of high self‐absorption in a continuous film, coupled with the inherent instability of PVSK materials, have hindered their use in this context. In this work, the viability of hybrid PVSK thin films as the active medium in planar LSCs is investigated. Using spectroscopic and photovoltaic measurements, variation of optical stability and device performance with different lead sources in the PVSK film precursors are monitored. The results display high optical efficiency in the range 15%–29% despite high self‐absorption losses, and the devices remain operational even after seven weeks in ambient conditions. Confirmed by Monte Carlo simulations, the superior performance is attributed to the high quantum yield and refractive index of the PVSKs. These results are encouraging not only for the implementation of PVSK thin films in LSCs, but additionally, for preparation of tandem devices to capture energy escaping as radiative exciton recombination in PVSK solar cells.

Tantalum Oxide Resistive Memory Devices By Ion Assisted Deposition

Nano-ionic resistive memory devices are of significant interest as a high density storage-class memory, and well as in neuromorphic accelerator computing. For both of these applications, a key challenge is cycle to cycle (temporal) and device to device write variability. Highly uniform films with evenly distributed concentrations of oxygen vacancies are desired for this purpose. The switchable resistive properties of these resistive memory devices have been typically fabricated from sub-stoichiometric tantalum pentoxide using reactive sputtering of Tantalum metal with a mixture of Argon and Oxygen, which does not result in a highly uniform film. Alternatively, by using annealed stoichiometric atomic layer deposited films combined with a reducing metal layer a more uniform film is obtained, but the oxygen vacancy distribution cannot be precisely controlled. Using Ion Assisted Deposition (IAD), we have successfully made memristor devices with a significant improvement in yield and a significant reduction in device performance variability. The IAD deposition approach involves e-beam evaporation of tantalum metal with a reactive beam of argon and oxygen ions impinging upon the growing film. Using this technique, the oxide formation occurs at the substrate resulting in better control over film stoichiometry. IAD is a popular technique for the deposition of oxide thin films in the optical coating industry, but this is the first known usage of this technique for stoichiometry control of ReRAM thin films. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000. Figure 1

Monitoring the Formation of a CH3NH3PbI3–xClx Perovskite during Thermal Annealing Using X‐Ray Scattering

Grazing incidence wide and small angle X‐ray scattering (GIWAXS and GISAXS) measurements have been used to study the crystallization kinetics of the organolead halide perovskite CH3NH3PbI3–xClx during thermal annealing. In situ GIWAXS measurements recorded during annealing are used to characterize and quantify the transition from a crystalline precursor to the perovskite structure. In situ GISAXS measurements indicate an evolution of crystallite sizes during annealing, with the number of crystallites having sizes between 30 and 400 nm increasing through the annealing process. Using ex situ scanning electron microscopy, this evolution in length scales is confirmed and a concurrent increase in film surface coverage is observed, a parameter crucial for efficient solar cell performance. A series of photovoltaic devices are then fabricated in which perovskite films have been annealed for different times, and variations in device performance are explained on the basis of X‐ray scattering measurements.

Study of Random Variation in Germanium-Source Vertical Tunnel FET

An optimally designed germanium-source vertical tunnel FET (V-TFET) is investigated using technology computer aided design simulation. Three consecutive band-to-band tunneling (BTBT) mechanisms (i.e., lateral, vertical, and additional vertical BTBT) are used in the V-TFET to enhance its performance as well as to maintain an average subthreshold slope below 60 mV/decade at 300 K. The impact of various V-TFET parameters on its performance is also investigated. Furthermore, the impact of threshold voltage variation ( $\sigma V_{\textrm {TH}}$ ) due to random variability [e.g., line-edge roughness (LER) and random dopant fluctuation (RDF)] on the performance of the V-TFET is studied. The LER in the V-TFET is found that the electric field is increased by the LER in the source region, resulting in the generation of lucky paths, which can lead to increase $\sigma V_{\textrm {TH}}$ . Without a gate-to-source overlap region in the V-TFET, RDF/LER-induced $\sigma V_{\textrm {TH}}$ is considerably increased by a lateral tunneling mechanism. As a result, the gate-to-source overlap region in the V-TFET is critical to enhancing the performance and designing a variation-aware V-TFET. Last but not least, field-induced quantum confinement leads to delay the onset voltage of the vertical BTBT, so that the device performance and process-induced random variation (especially, RDF) are significantly deteriorated.

(Invited) Pristine Electronics Grade Semiconducting Carbon Nanotubes By Switching the Rigidity of the Wrapping Polymer Backbone

In order to widely use single-walled carbon nanotubes (SWCNTs) as the semiconducting material in electronic devices, it is essential to separate the desirable semiconducting SWCNTs from as-synthesized electronically heterogeneous mixtures of metallic (m-) and semiconducting (s-) SWCNTs. Among the sorting methods developed, polyfluorene polymers have been studied as semiconducting-selective agents with selectivity for chirality, diameter and electronic type. Developing an understanding for the factors that lead to strong selective interactions between the conjugated polymer and the semiconducting tubes is evolving but far from complete. We choose a commonly used commercially available polyfluorene derivative PFO-BPy as a model polymer to directly probe the effect of chain rigidity on the wrapping/unwrapping process on the s-SWCNTs. Our choice of this model system is based on its commercial availability, outstanding sorting selectivity, availability of functional groups in the backbone to alter rigidity, and recent device results. Recently, we demonstrated the extraordinarily electronic-type selectively of the polyfluorene derivative PFO-BPy by measuring the on/off ratio of FETs, where zero metallic nanotubes were encountered in the measurement of more than 5,000 s-SWCNTs.1-3 Using the similar polymer poly(9,9-dioctylfluorene-2,7-diyl) (PFO), Bindl et al., demonstrated that even after several aggressive rinsing steps to remove free or excess polymer using ultracentrifugation a significant amount of PFO remained bound to the SWCNT. 4 These remaining polymer residues are expected to increase the contact resistance at the metal-nanotube interface of SWCNT FETs, ultimately limiting the conductance of these FETs at sub-100 nm channel lengths. A more complete removal of adsorbed polymer residues from the SWCNT surface is one possible approach towards improving contact resistance and reducing variation in device performance.5 Recently we demonstrated6 an effective yet simple and mild method to remove post-sorting, and the wrapping PFO-BPy copolymer from the surface of s-SWCNTs by switching the backbone rigidity. We used chelation chemistry to complex pentacarbonylrhenium chloride (Re (CO)5Cl) to the bipyridine (BPy) moiety in the wrapping copolymer backbone. We showed the effectiveness of the chelation chemistry on both large and small diameter tubes. The chain-stiffness of the PFO-BPy changes upon complexation, likely providing the driving force to overcome the π-π and electronic interactions7 which adhere the polymer to the nanotube. Optical absorbance, X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, and large-scale molecular dynamics simulations were used to characterize the extent of PFO-BPy removal and configurational changes to the PFO-BPy after Re(CO)5Cl complexation (PFO-BPy:Re).The ability to switch the rigidity of the PFO-BPy in order to unwrap from the nanotubes opens up the door to new design strategies where specific functional groups can be placed on the polymer backbone to chemically alter the rigidity. Here, we present recent results on direct experimental measurements of changes in stiffness of the polymer backbone and its aggregation state upon metal complexation. 1. Brady, G. J.; Joo, Y.; Roy, S. S.; Gopalan, P.; Arnold, M. S. Appl. Phys. Lett. 2014, 104, (8), 083107. 2. Joo, Y.; Brady, G. J.; Arnold, M. S.; Gopalan, P. Langmuir 2014, 30, (12), 3460-3466. 3. Mistry, K. S.; Larsen, B. A.; Blackburn, J. L. ACS nano 2013, 7, (3), 2231-2239. 4. Bindl, D. J.; Shea, M. J.; Arnold, M. S. Chem. Phys. 2013, 413, 29-34. 5. Wang, W. Z.; Li, W. F.; Pan, X. Y.; Li, C. M.; Li, L. J.; Mu, Y. G.; Rogers, J. A.; Chan-Park, M. B. Adv. Funct. Mater. 2011, 21, (9), 1643-1651. 6. Joo, Y.; Brady, G. J.; Shea, M. J.; Oviedo, M. B.; Kanimozhi, C.; Schmitt, S. K.; Wong, B. M.; Arnold, M. S.; Gopalan, P. ACS Nano 2015, 9, (10), 10203-10213. 7. Nish, A.; Hwang, J. Y.; Doig, J.; Nicholas, R. J. Nature nanotechnology 2007, 2, (10), 640-6.

Thermal Method to Reduce the Polysilicon Resistance for Deep Submicron Integration Process

In this paper, a new annealing process to reduce polysilicon resistance without implant dosage adjustment has been proposed. With increasing the annealing temperatures, polysilicon grain size increases and causes the polysilicon resistance reduction. After annealing in inert gas ambient at 950°C for 5 min, the polysilicon resistance can be obviously reduced more than 7.7%, comparing to the 800°C for 5 min annealing process. And the threshold voltage and saturation current characteristics of submicron MOS device can be maintained almost same as before, due to the minor doping profile variations. Therefore, this new annealing process without device performance variations can be a candidate to reduce the polysilicon resistance applied to deep submicron integration circuit process.

Experimental Study of a Hybrid Small-Signal Parameter Modeling and Extraction Method for a Microoptoelectronic Device

In the device performance variation and control for microdevices, accurate models are critical for predicting dc behaviors as well as high-frequency behaviors. Thus, acquiring the characteristics of an optoelectronic device is essential for estimating its application to high-throughput control systems. In particular, we present an experimental and analytical investigation for extracting the parameters and intrinsic properties of an optoelectronic microdevice. Our study utilizes a near-infrared, InGaAsP buried heterostructure, multiquantum well distributed-feedback laser. We utilize a modified frequency response model and the conventional method of subtracting frequency responses in two different bias currents above the laser threshold current to attain the resonance frequency and damping factor using a simple four-parameter curve-fitting procedure. With this method, we were able to acquire the intrinsic properties of the laser and its frequency response. In addition, the series resistance, which is drawn directly from a modified current–voltage ( I – V ) curve, can explicitly reflect the operation of the laser below and above the threshold current. The parasitic capacitance was found by comparing the measured and extracted intrinsic frequency responses. Our extracted results agree well with previously published results.

Data-driven stochastic models for spatial uncertainties in micromechanical systems

Accurate uncertainty quantification in engineering systems requires the use of proper data-driven stochastic models that bear a good fidelity with respect to experimentally observed variations. This paper looks at a variety of modeling techniques to represent spatially varying uncertainties in a form that can be incorporated into numerical simulations. In the context of microelectromechanical systems, we consider spatial uncertainties at the device level in the form of surface roughness and at the wafer level in the form of non-uniformities that arise as a result of various microfabrication steps. We discuss methods to obtain roughness characterization data ranging from the use of a simple profilometer probe to imaging-based techniques for the extraction of digitized data from images. We model spatial uncertainties as second-order stochastic process and use Bayesian inference to estimate the model parameters from the input data. We apply the data-driven stochastic models generated from this process to micromechanical actuators and sensors in which these spatial uncertainties are likely to cause significant variation. These include an electrostatically-actuated torsion-spring micromirror, an electromechanical comb-drive actuator and a pressure sensor with a piezoresistive strain gauge. We show that the performance of these devices is sensitive to the presence of spatial uncertainties and a proper modeling of these uncertainties helps us make reliable predictions about the variation in device performance. Where data is available, we even show that the predicted variation can be validated against experimental observations, highlighting the significance of proper stochastic modeling in the analysis of such devices.

Strained p-Channel MOSFET Fabrication Challenge and Perspective for the 28-Nm Technology Node and Beyond

Carrier mobility enhancement technique was introduced to ULSI manufacture since 90-nm technology node. As one of promising mobility enhancement techniques, the strain/stress at the channel region of metal-oxide-semiconductor field effect transistors (MOSFETs) modulates the lattice constant and band structure of silicon then enhances the hole/electron mobility. [1] The high mobility gives high source injection velocity into the quasi-ballistic transport channel which can provide high drive current and high circuit speed of MOSFETs. [2] Among a great variety of mobility enhancement techniques by applying stress to induce appropriate strain in the p-channel region, forming embedded epitaxial Si1-xGex with recessed Source/Drain (S/D) structure has been reported as one powerful technique. [3] The Sigma-shaped silicon recess profile is applied before epitaxial Si1-xGexgrowth, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. [4] In this manuscript, we utilized one-step and two-step dry etch process with the same alkaline solution wet etch to form Sigma-shaped silicon recess profile for the planar p-channel MOSFETs. After comparing the recess depth loading correlated to the pitch of gate electrodes (Table 1), we also studied the tunable capability and limitations on tip depth, tip proximity and total depth of Sigma-shaped trench for these two different dry etch processes. The strict profile control of Sigma-shaped profile is not only led by the device performance variation demand but also needed to get the excellent epitaxial Si1-xGex crystallinity. Besides that, Si-C bond on the trench surface could inhibit the epitaxial Si1-xGex growth, thus resulting in defects on S/D area. We proved that high H2 volume ash process could effectively remove the Si-C bond at trench surface and greatly reduce the Si1-xGexdefect counts. (Fig. 1) Recently, the further down-scaling of planar MOSFETs technology is facing a serious physical limitation which results in short-channel effects (SCEs). Multiple-gate FETs or Fin structure FETs are already adopted in the fabrication process for the excellent control of SCEs from 20-nm technology node. Unlike the conventional planar transistor, a significant portion of the drain current is conducted along the fin sidewalls in FinFETs. Therefore, to realize a large mobility enhancement, the strain/stress techniques of FinFETs should be significantly different from embedded Si1-xGex techniques of traditional planar devices. The Pi-shaped Si1-xGex (Π-Si1-xGex) should be induced to encapsulate the silicon on the top and sidewalls of the narrow fins. [5] In this work, the Π-Si1-xGex stressors should be grown on the top and sidewalls of fins in the S/D regions of p-channel FinFETs. However, due to the loading effect of traditional silicon nitride (SIN) spacer etch, the epitaxial Si1-xGex growth could be hindered by the existence of SIN spacer stringer at the sides of the fin in some special pattern density area. To solve this issue, multi-cycle SIN etch process was attempted in the spacer open step. Compared with the conventional etch process, the multi-cycle SIN etch process delivers the excellent control of spacer pull back loading at universal pattern density area. (Fig. 2) In order to protect the SIN capping layer on the gate top corner and clearly remove the SIN spacer at the top area of fins, the gas types, gas ratio and other parameters are carefully optimized in SIN spacer etch process. We successfully decoupled the trade-off line of capping layer protection and the SIN spacer pull back. Additionally, by balancing the isotropic and anisotropic recess parts in the whole process, we demonstrated the recessed fin structure with flat and smooth surface on the top area, which would be benefit for future good crystalline and well controlled Π-Si1-xGexgrowth. (Fig. 3) ACKNOWLEDGMENT This work was partially sponsored by Program of Shanghai Technology Chief Scientist (B type).

Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance

One of the key challenges in scaling beyond 10-nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> , inhibits V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> scaling. In this paper, we present a comprehensive study of process variations and sidewall roughness (SWR) effects in silicon (Si) bulk n-/p-FinFETs, In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As bulk n-FinFETs, germanium (Ge) bulk p-FinFETs, and gallium antimonide-indium arsenide (GaSb-InAs) staggered-gap heterojunction n-/p-tunnel FETs (HTFETs) using 3-D Technology Computer Aided Design numerical simulations. According to the sensitivity study, FinFET and tunnel FET (TFET) device parameters are highly susceptible to fin width, W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FIN</sub> , and ultrathin body thickness, T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> , variations, respectively. TFETs show higher variation in device performance than FinFETs. A Monte Carlo study of SWR variation on nand p-FinFETs shows higher 3σ(VT Lin) of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As bulk nand Ge bulk p-FinFETs than their Si counterparts. Furthermore, to study the variation impact on memory circuits, we simulate 6T and 10T static random access memory (SRAM) cells with FinFETs and HTFETs, respectively. The probability distribution of read failure in SRAM cells at different supply voltages, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CC</sub> , shows that HTFETs require 10T SRAM cell architecture and less than 4% variation in T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> for their V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CCmin</sub> to approach 200 mV.

The Impact of Junction Doping Distribution on Device Performance Variability and Reliability for Fully Depleted Silicon on Insulator With Thin Box Layer MOSFETs

In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performance and hot carrier induced degradations have also been examined. Junction doping dose of LDD/halo affects the effective channel length, parasitic source/drain resistance, and channel mobility. High junction doping dose enhances the device's performance but degrades device stability and reliability. Compared to high junction doping FDSOI nMOSFET, low junction doping device has lower device variability, better symmetry, and reliability, but suffers lower channel mobility and device driving capability.

Spectroscopic Ellipsometry Applied in the Full p-i-n a-Si:H Solar Cell Device Configuration

Assessment of the performance of single-junction hydrogenated amorphous silicon (a-Si:H) p-i-n configuration solar cells has been developed with a combination of real-time spectroscopic ellipsometry (RTSE) and current-voltage (I-V) measurements. For each layer, RTSE measurements enabled the determination of thickness and optical properties in the form of the complex dielectric function (e = e 1 + ie 2 ) spectra. RTSE tracked changes in a as a function of depth and was used to extract profiles in the i-layer bandgap and crystallite fraction in the n-layer. Through mapping I-V characteristic measurements, spatial variations in device performance were determined. By comparing individual devices at the location of the RTSE beam spot, the influence of a and thickness for each layer on device performance was identified through simulations of quantum efficiency yielding the shortcircuit current. This study compares two devices prepared with different superstrate preheating processes and finds that the combination of RTSE and I-V measurements along with quantum efficiency simulations were able to identify plasma damage to the transparent conducting oxide as the likely cause for variation in device performance. This comparison serves as one example of how the optically obtained information, such as thickness and a for each layer, can be used to understand the final device performance.

Experimental and Theoretical Investigation of Minimization of Forming-Induced Variability in Resistive Memory Devices

ABSTRACTResistive memory materials and devices (often called memristors) are an area of intense research, with metal/metal oxide/metal resistive elements a prominent example of such devices. Electroforming (the formation of a conductive filament in the metal oxide layer) represents one of the often necessary steps of resistive memory device fabrication that results in large and poorly controlled variability in device performance. In this contribution we present a numerical investigation of the electroforming process. In our model, drift and Ficks and Soret diffusion processes are responsible for movement of vacancies in the oxide material. Simulations predict filament formation and qualitatively agreed with a reduction of the forming voltage in structures with a top electrode. The forming and switching results of the study are compared with numerical simulations and show a possible pathway toward more repeatable and controllable resistive memory devices.

Effect of copper oxide oxidation state on the polymer-based solar cell buffer layers.

Transporting buffer layers are important components of polymer-based organic photovoltaic devices. In this study, we have investigated the effects of the oxidation state in copper oxide based buffer layer in conjunction to its role in device performance. We have shown that variation in the oxidation state affects the band alignment and built-in voltage of the device, therefore leading to variation in device performance. Specifically, the fully oxidized copper oxide buffer layer has a valence band position at 5.12 eV, much closer to the highest occupied molecular orbital of poly(3-hexylthiophene-2,5-diyl) (P3HT) (∼5.2 eV), giving a best fill factor and efficiency at 57% and 4.06%, respectively. Lastly, we also demonstrate significant enhancement in device stability, with power conversion efficiency maintained at 75% of the original value even after 40 days, and propose a strategy for recovering the device performance based on the observed property of the oxide buffer layer.

Reliability assessment of MEMS switches for space applications: laboratory and launch testing

A novel combination of ground-based and flight tests was employed to examine the reliability of capacitive radio-frequency microelectromechanical switches for use in space applications. Laboratory tests were initially conducted to examine the thermomechanical effects of packaging and space-like thermal stresses on the pull-in voltage of the devices; during this process it was observed that operational stability is highly dependent on the geometrical design of the switch and this must be taken in to account during the design stage. To further expose the switches to acceleration levels experienced during a space mission, they were launched on board a sounding rocket and then subjected to free-fall from a height of over 1.3 km with a resulting impact of over 3500g. Post launch analysis indicates that the switches are remarkably resilient to high levels of acceleration. Some evidence is also present to indicate that time-dependent strain relaxation in die attach epoxy materials may contribute to minor variations in device shape and performance.

Depth profiling organic light-emitting devices by gas-cluster ion beam sputtering and X-ray photoelectron spectroscopy

The composition depth profile in organic light-emitting devices (OLEDs) is investigated using X-ray photoelectron spectroscopy (XPS) coupled with gas-cluster Ar-ion beam milling (Ar-GCIB). The XPS technique gives precise information about the surface chemistry of the organic thin films and is capable of differentiating the various charge transport, host and guest materials used in an OLED. The use of large Ar ion clusters (∼1500–2500atoms/cluster) in the milling process allows for small amounts of the organic thin film to be sputtered away without contaminating the surface or damaging the underlying material chemistry. By probing OLEDs as a function of depth, key parameters including emissive layer composition and interface quality can be assessed directly. It is found that the depth profile for graded-composition emissive layer OLEDs closely matches the intended deposition profiles, maintaining both the composition gradient and the intended endpoint compositions. The ability to resolve and correlate subtle changes in film composition to variations in device performance will help inform efforts in device design, while also serving as a diagnostic tool to better understand the mechanisms for device degradation and failure.

Plant simulation and operation optimisation of SMR plant with different adjustment methods under part-load conditions

A plant simulation model of SMR (single mixed refrigerant cycle) plant which considers the performance variations of devices under different working conditions is established. It could be used to predict the performance variations of an SMR plant under part-load, and other working conditions. The operational optimisation based on plant simulation is conducted for SMR plant with different load adjustment facilities. The constraint condition uses a penalty function method and the Box method is applied for solution optimisation. The results show that the frequency conversion method could achieve the best adjustment performance and the composition optimisation is significant for the frequency conversion method, especially when the load is below 40%. The operational strategy giving the lowest energy consumption for SMR plant with different adjustment methods under part-load conditions was discussed and the efficiency of the MR compressor is regarded as the prime influence thereon.

Raman Characterization of Poly-Si Channel Materials for 3D Flash Memory Device Applications

Three dimensional (3D) vertical NAND (V-NAND) flash technology has been actively investigated. [1] 3D NAND architectures offer one of the best combinations of device performance, memory density, power consumption and manufacturing cost. All major memory device manufacturers are actively pursuing development of commercially viable devices. Development of bit cost scalable (BiCS) NAND technology is very important from both technology and commercialization points of view.Device scaling was achieved by vertical staking of thin film transistors (TFTs) in contrast to the conventional planar device scaling techniques relying on advances in lithography. Poly-Si is used as channel materials in 3D V-NAND flash memory devices. Control of both poly-Si grain size and grain size distribution is very important for tight control of device yield and performance variations.For poly-Si channel fabrication, amorphous Si (a-Si) film is deposited in the channel region and then converted to poly-Si by thermal annealing. To achieve desired properties of the poly-Si channel, grain size, resistivity, mobility and interface quality must be carefully monitored and controlled. One of the basic parameters of the poly-Si channel is grain size. Smaller grains lower in channel carrier mobility while larger grains increase device performance variations. The grain size and its distribution have to be optimized for the best device performance. Development of proper in-line characterization techniques for poly-Si grain size, after thermal annealing, is strongly desired.In this paper, Raman spectroscopy was used for characterizing poly-Si after thermal annealing of chemical vapor deposited (CVD) thin a-Si films on SiO2/Si wafers. The a-Si films on SiO2/Si wafers were annealed in a single wafer rapid thermal furnace (SRTF-300 system [4, 5]) in the temperature range of 600 ~ 1050oC under various ambient gases.Systematic change of Raman spectra, indicating crystallization of a-Si films and grain growth of poly-Si with annealing temperature increase was measured (Fig. 1.) using an MRS-300 system. [6] As deposited a-Si/SiO2/Si showed one sharp peak from the Si wafer at ~ 520.3cm-1 and one broad peak centered at ~ 480cm-1 corresponding to a-Si. After thermal annealing, the a-Si peak decreased in intensity and transformed into new peaks at ~ 495 and ~ 515 cm-1, corresponding to poly-Si. The poly-Si peaks increased and sharpened as the annealing temperature increased. The change of Raman spectra indicates the degree of polycrystallization and grain growth under different annealing conditions. Figures 2 and 3 showed the Raman spectra from the annealed samples and their deconvolution results. Detailed Raman characterization, as a function of annealing temperature and type of ambient gas, will be reported at the conference.

Two-Transistor Current-Biased Voltage-Programmed AM-OLED Pixel

A new two-transistor pixel circuit in a current-biased voltage programming mode for active matrix-organic light emitting diode displays is proposed. The proposed circuit features a fixed current source and a conventional data line. The former offers a moderate bias current to compensate for the device performance variation or degeneration, and the latter provides pixels with voltage signals. It is demonstrated that both accurate and fast compensations can be realized in the proposed pixel circuit.