Thermal Method to Reduce the Polysilicon Resistance for Deep Submicron Integration Process

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In this paper, a new annealing process to reduce polysilicon resistance without implant dosage adjustment has been proposed. With increasing the annealing temperatures, polysilicon grain size increases and causes the polysilicon resistance reduction. After annealing in inert gas ambient at 950°C for 5 min, the polysilicon resistance can be obviously reduced more than 7.7%, comparing to the 800°C for 5 min annealing process. And the threshold voltage and saturation current characteristics of submicron MOS device can be maintained almost same as before, due to the minor doping profile variations. Therefore, this new annealing process without device performance variations can be a candidate to reduce the polysilicon resistance applied to deep submicron integration circuit process.