Device Dimensions Research Articles

Improving vertical solar still performance for efficient Desalination: Investigating the influence of Wick, condensate plate and device dimensions

Access to sustainable energy sources and clean water remain two of the most significant challenges in the modern world. Fortunately, desalination can be achieved using a variety of renewable energy sources, with solar energy being a notable option. There has been a noticeable increase in interest in the vertical solar still (VSS) as a popular desalination technique in recent years. The performance of VSS is examined in this article in relation to a several variables, including the wick, the wettability of the condensate plate surface, and device dimensions. According to the study's findings, selecting an appropriate wick is essential for ensuring optimum water distribution on the heat absorber surface, thereby enhancing the effectiveness of the Vertical Solar Still (VSS). In comparison to gauze, cotton emerges as a superior wick, contributing to a noteworthy 5.1 % improvement in device performance. The performance of the VSS is significantly influenced by the contact angle of the condensate surface plate, a glass plate (contact angle of 5) yields 34 % more freshwater than a superhydrophobic plate (contact angle of 140). This study also shows that the dimensions of the vertical solar still (VSS) are significantly impactby the properties of the condensate plate and wick. Specifically, the most efficient VSS performance is attained when the dimensions are set at 32 cm × 30 cm.

The Trade‐Off between Transconductance and Speed for Vertical Organic Electrochemical Transistors

AbstractThe high transconductance gm of organic electrochemical transistors (OECTs) has received widespread attention and made OECTs a valid candidate for wearable sensor systems. However, the large transconductance is often accompanied by large switching time constants, τ, making the transconductance an imperfect benchmark. For a fair assessment, the ratio of transconductance to switching time constant has to be considered instead of any single parameter in isolation. One approach put forward to optimize OECTs is a vertical design, in which the channel length can be scaled into the sub‐micrometer regime. Here, a new vertical device geometry is proposed, in which the active volume of the mixed conductor is confined to a small cavity between source and drain, yielding excellent performance and reproducibility. It is shown that this approach yields optimized ratios instead of maximized transconductance only. However, this scaling is effective only in a small range of device dimensions and requires careful optimization of the device to not be limited by parasitic effects such as excess volume of the mixed conductor or parasitic series resistances. Overall, the design considerations discussed here provide new guidelines to optimize OECTs, not only for high transconductance but for operation at high frequencies as well.

Improving the Performance of Selective Solid-State Nanopore Sensing Using a Polyhistidine-Tagged Monovalent Streptavidin.

Solid-state (SS-) nanopore sensing has gained tremendous attention in recent years, but it has been constrained by its intrinsic lack of selectivity. To address this, we previously established a novel SS-nanopore assay that produces translocation signals only when a target biotinylated nucleic acid fragment binds to monovalent streptavidin (MS), a protein variant with a single high-affinity biotin-binding domain. While this approach has enabled selective quantification of diverse nucleic acid biomarkers, sensitivity enhancements are needed to improve the detection of low-abundance translational targets. Because the translocation dynamics that determine assay efficacy are largely governed by constituent charge characteristics, we here incorporate a polyhistidine-tagged MS (hMS) to alter the component detectability. We investigate the effects of buffer pH, salt concentration, and SS-nanopore diameter on the performance with the alternate reagent, achieve significant improvements in measurement sensitivity and selectivity, and expand the range of device dimensions viable for the assay. We used this improvement to detect as little as 1 nM miRNA spiked into human plasma. Overall, our findings improve the potential for broader applications of SS-nanopores in the quantitative analyses of molecular biomarkers.

Gate Electrode Work Function Engineered Nanowire FET with High Performance and Improved Process Sensitivity

MOSFETs have been used in integrated circuits for a long time. These were replaced by FinFET’s in 2011. But for short-channel devices, FinFET’s have low performance due to various effects like velocity saturation, hot carrier effect, drain-induced barrier lowering, channel length modulation, fringing field effect, sub-threshold conduction, threshold voltage roll-off, etc. Gate All Around FET (GAA FET) is the best device that will replace the FinFET’s. Therefore, during the fabrication process, it is crucial to investigate the effects of process variations caused by changes in device dimensions. This research discusses the performance of the proposed device due to process variations. The effect of changes in radius, gate oxide thickness, gate length, and channel doping on GAA FET has been discussed in detail.

Climate impacts of digital use supply chains

Information and communications technology (ICT) has become an indispensable part of our lives. Prior research on climate impact of ICT devices and services mostly makes use of life cycle assessment and energy modeling frameworks focused on embodied greenhouse gas (GHG) emissions. Because these perspectives emphasize the GHGs emissions associated with the construction and distribution of digital devices along production supply chains, not much is known about the GHGs emissions monitored or facilitated by digital device use. In this study, we propose the concept of digital use supply chains (DUSCs) as an orthogonal dimension of digital devices’ life cycle. DUSC refers to the production activities and resource consumption recorded by digital devices. We propose a framework to conceptualize and quantify digital behavior-related GHGs emissions through use of the Screenomics paradigm, where users’ digital screen data are unobtrusively collected moment-by-moment. Through Screenomics’ granular recording of users’ digital behavior, we evaluate behavior-based GHGs emissions traced by the digital devices. DUSC connects individual’s digital behaviors to their global climate change impact, contributing to a more nuanced and complete evaluation of the climate impacts of the digital economy. Our single-case study indicates the estimated scale of the GHGs emissions linked to a user’s one-day digital activities could be three orders of magnitude (1000 times) higher than the emissions associated with the device life cycle alone. DUSC could enable climate change mitigation at a meaningful, actionable level through personalized educational or behavior change programs, and also facilitate novel data-driven feedback loops that may provide digital device users with insights into their personal climate impacts. Recognition and future study of DUSC could accelerate the quantification and standardization of a ‘carbon handprint’ of digital devices and create positive climate impacts from digital products and services.

Roadmap for Optical Metasurfaces.

Metasurfaces have recently risen to prominence in optical research, providing unique functionalities that can be used for imaging, beam forming, holography, polarimetry, and many more, while keeping device dimensions small. Despite the fact that a vast range of basic metasurface designs has already been thoroughly studied in the literature, the number of metasurface-related papers is still growing at a rapid pace, as metasurface research is now spreading to adjacent fields, including computational imaging, augmented and virtual reality, automotive, display, biosensing, nonlinear, quantum and topological optics, optical computing, and more. At the same time, the ability of metasurfaces to perform optical functions in much more compact optical systems has triggered strong and constantly growing interest from various industries that greatly benefit from the availability of miniaturized, highly functional, and efficient optical components that can be integrated in optoelectronic systems at low cost. This creates a truly unique opportunity for the field of metasurfaces to make both a scientific and an industrial impact. The goal of this Roadmap is to mark this "golden age" of metasurface research and define future directions to encourage scientists and engineers to drive research and development in the field of metasurfaces toward both scientific excellence and broad industrial adoption.

Dynamical Mechanism for Reaching Ultrahigh Voltages from a Falling Droplet

AbstractRecent experiments have demonstrated an extremely high output voltage of 260 V by impinging droplets on an electret surface with top and back electrodes. However, the mechanism underlying the generated high voltage remains elusive. Through high‐speed imaging of the impinging water droplet, it is found that the recorded voltage is proportional to the change rate of contact length l between the droplet and the top electrode over time, that is, dl/dt. By combining an electrostatic model with multi‐physics simulations, the time‐dependent charge distribution on the top electrode is analytically described as a function of several key factors pertaining to the spreading dynamics of droplet and the geometrical dimensions of device. These results show that the high voltage originates from the accumulation of charge in the spreading droplet and the ensuing instantaneous discharge upon high‐speed contact with the top electrode. Using the model‐optimized parameters, the experimentally generated voltage from a falling 64 µL droplet with a 2 mm salt can be boosted to 1030 V, giving rise to an energy conversion efficiency as high as 3.3%. This conversion efficiency will further increase by 14 times if the surface charge density of the electret can be enhanced to its limit using state‐of‐the‐art fabrication techniques.

Influence of surface acoustic wave (SAW) on nanoscale in-plane magnetic tunnel junctions

The use of voltage induced strain to switch magnetic tunnel junctions (MTJs) is a promising solution for reducing the switching energy in MRAM technologies. The MTJ is integrated with a piezoelectric layer to generate the strain. A very thin layer is needed to switch with small voltages and small energy dissipation. It is challenging to synthesize ultrathin piezoelectric layers that retain a high degree of piezoelectricity. An alternate approach is to use time-varying strain generated by a surface acoustic wave (SAW). This approach does not require a thin piezoelectric layer since the SAW is confined to the surface of the layer. In this study, we fabricated in-plane MTJs on piezoelectric LiNbO3 substrates and used IDTs to generate the SAW signal within the substrate. Our results showed that the SAW signal had a significant influence on the resistance and the tunneling magnetoresistance (TMR) ratio of the MTJs. The influence was much less significant in nanometer size MTJs than in micrometer sized ones. Most surprisingly, the SAW signal caused the tunneling magnetoresistance ratio (TMR) to drop below zero for the micrometer size MTJ, meaning that the antiparallel resistance RAP is temporarily less than the parallel resistance RP under SAW excitation. Our results provide insight into the dynamic behavior of MTJs under periodic strain and the dependence of this behavior on the device dimensions as they are scaled down to nanometer sizes.

Reliability Thermal Design, Simulation and Experimental Verification of Electronic Monitoring Unit for Magnetic Resonance System

The monitoring unit used in the nuclear magnetic resonance system, as an important unit of the system, faces a high thermal risk during its entire life cycle. This paper ensures the high efficiency and reliability of the thermal design of the product module from the two dimensions of structural design and device derating design. In order to reduce the risk of thermal design of electronic modules and comprehensively verify the effectiveness of thermal design of electronic modules, the design verification is carried out by combining simulation and experiment. In the simulation process, by establishing a thermal simulation model at the circuit board level, the crustal temperature of the core device is numerically calculated, and the index is compared with the thermal design index value and the test value, on the one hand, to verify the correctness of the simulation model. On the other hand, the validity of thermal design is verified. In the testing process, a thermal test platform for product modules is built, and the thermal characteristics test values of the core components of the module under extreme electrical conditions are obtained, and the corresponding conversion methods are used to predict the thermal performance and thermal design margin of the product at different altitudes. The results show that the electronic module can meet the thermal design requirements in terms of structural design and derating design of core components, and can ensure that the product module can work safely and reliably during the entire life cycle of the NMR system.

Novel nanocomposite-superlattices for low energy and high stability nanoscale phase-change memory

Data-centric applications are pushing the limits of energy-efficiency in today’s computing systems, including those based on phase-change memory (PCM). This technology must achieve low-power and stable operation at nanoscale dimensions to succeed in high-density memory arrays. Here we use a novel combination of phase-change material superlattices and nanocomposites (based on Ge4Sb6Te7), to achieve record-low power density ≈ 5 MW/cm2 and ≈ 0.7 V switching voltage (compatible with modern logic processors) in PCM devices with the smallest dimensions to date (≈ 40 nm) for a superlattice technology on a CMOS-compatible substrate. These devices also simultaneously exhibit low resistance drift with 8 resistance states, good endurance (≈ 2 × 108 cycles), and fast switching (≈ 40 ns). The efficient switching is enabled by strong heat confinement within the superlattice materials and the nanoscale device dimensions. The microstructural properties of the Ge4Sb6Te7 nanocomposite and its high crystallization temperature ensure the fast-switching speed and stability in our superlattice PCM devices. These results re-establish PCM technology as one of the frontrunners for energy-efficient data storage and computing.

Catalytic Metal‐Gated Nano‐Sheet Field Effect Transistor and Nano‐Sheet Tunnel Field Effect Transistor Based Hydrogen Gas Sensor‐ A Design Perspective

AbstractIn this work, for the first time, the catalytic metal gate (CMG) based nanosheet Field Effect Transistor (NSFET) and nanosheet Tunnel Field Effect Transistor (NSTFET) are proposed for nano‐scale device dimensions, and the different design aspects of catalytic metal gate (CMG)‐based transduction for Hydrogen (H2) sensing are extensively investigated using numerical device simulation. The influence of applied biasing conditions and structural parameter specifications on the sensing performance of CMG‐NSFET and CMG‐NSTFET are methodically analyzed from device electrostatics and carrier transport mechanisms. Furthermore, the relative maximum sensitivity variations with H2‐partial pressure, ambient temperature, and the presence of ambient Oxygen are comprehensively studied. The study reveals that compared to CMG‐NSFET, the CMG‐NSTFET demonstrates a high immunity against bias and doping variations, with a notably higher (> 50%) sensitivity within low H2 partial pressures (10−15 – 10−10 Torr). Next, the sensing performance of CMG‐NSTFET is systematically optimized through a band‐gap and gate‐stack engineering approach, leading to a 180% to 650% sensitivity improvement from lower (10−15 Torr) to higher (10−5 Torr) range of H2 partial pressure. Finally, the performance of optimized CMG‐NSFET and CMG‐NSTFET are extensively benchmarked against other reported nanostructured CMG‐FET and TFET‐based H2 gas sensors, exhibiting a notably higher sensitivity in the proposed sensors.

Medical Device-Related Pressure Injury Care and Prevention Training Program (DevICeU): Effects on intensive care nurses' knowledge, prevention performance and point prevalence

ObjectiveTo determine the effect of the training given to intensive care unit (ICU) nurses to prevent medical device-related pressure injuries (MDRPIs) on nurses' knowledge levels, their prevention performance, and the point prevalence (PP) of MDRPIs. Research Methodology/DesignA pre-post test intervention study without a control group. SettingThe study was conducted between May and July 2023 with ICU nurses in three phases: pre-training phase (E0) (104 nurses, 116 patients), training implementation phase (E) and post-training phase (E1) (89 nurses, 120 patients). Main Outcome MeasuresThe data were collected by using the Patient (E0, E1) and Nurse (E0) Characteristic Forms, MDRPI Follow-up and Prevalence Form (E0, E1), D.E.V.I.C.E Performance Observation Checklist (E0, E1), MDRPI Knowledge Assessment Questionnaire (E0, E1), Braden Pressure Ulcer Risk Assessment Scale (E0, E1), Pressure Injury Grading Form (E0, E1), and Feedback Form about the Training Process (E). ResultsThe mean MDRPI knowledge score of the nurses increased significantly from E0 to E1 (13.23 ± 1.43 vs. 20.02 ± 1.30, p = 0.001), with the highest improvement in the staging and prevention themes. Nurses’ MDRPI prevention performance increased significantly from E0 to E1 (2.15 ± 1.01 vs. 11.17 ± 1.65, p = 0.001). There was a significant difference between the PP rate at E0 (61.2 %) and E1 (27.5 %) (p = 0.001). ConclusionThe study indicated that the training on MDRPIs given to ICU nurses increased their knowledge and prevention performance and decreased the prevalence of MDRPIs. However, further studies with a larger sample size are needed to confirm these findings. Implications for clinical practiceSince MDRPIs have more complex staging and prevention practices than conventional PIs, they require the adoption of a training approach that includes visual materials and practical methods in addition to theoretical knowledge. Accurate definitions of medical device dimensions and fixation, skin assessment, and prevention practices will lead to the desired outcome of reducing MDRPIs in ICUs.

Frequency encoded tristate Pauli X-gate using SOA assisted photonic band gap crystal

The quantum optical tristate Pauli-X gate can broadly be used due to its very fast speed of operation up to THz order, very fast information processing rate, and a wide domain of application. This Pauli X-gate is also important as it can undergo inversion operation. In this proposed scheme, the quantum tristate Pauli-X logic gate has been constructed by a closely packed square lattice of 2D air photonic band gap crystal (PhCs) composed of GaAsInP-dopped rods. The photonic band gap crystal-based tristate Pauli-X gate is performed also as an all-optical reversible quantum logic gate which has the character of low-powered output, very fast speed and a densely packed design structure. This photonic crystal-based structure is also verified by simulation experiment that this proposed scheme performs as the path of two input signals are cross-exchanged to one another at the output, retaining the path of the other input signal same. In this paper, the frequency encoding technique is used in all the designs to establish the logic of all-optical tristate Pauli X-gate towards the need of obtaining a three-input-three-output inversion system. The frequency encoding technique and the photonic crystal-based three Semiconductor Optical Amplifiers (pc-SOAs) are used here in all the schemes to establish the logic of the tristate Pauli-X gate scheme. Tristate Pauli-X gates have been designed and analyzed by Finite-Difference Time-Domain (FDTD) and Plane Wave Expansion (PWE) techniques. The Plane Wave Expansion (PWE) technique is used here in each system for determining the frequency range of band gap structure of transverse electric (TE) mode in the units of μm-1. All of these devices perform within the frequency range 0.629818≤ω2πc≤0.888037 and 1.17551≤ω2πc ≤ 1.34921 μm-1. The wafer dimension of each photonic band gap crystal-based device is 19.20 μm (length) × 16.20 μm (width) providing a very fast response time and very fast information handling (bit rate) capacity, which is found good for these THz Photonic crystal devices. Simulation results show that the proposed gate provides a response period of 0.291 ps and a bit rate of 3.44 Tbps, operating with a low input power of 3.45 mW. The reversible gate exhibits a response period of 0.289 ps and a bit rate of 3.46 Tbps, operating also with a low input power of 2.70 mW. Additionally, the alternative Pauli-X gate demonstrates a response time of 0.291 ps and a bit rate of 3.44 Tbps, operating with a low input power of 2.83 mW.

Evaluating performance of vortex-diode based hydrodynamic cavitation device scale and pressure drop using coumarin dosimetry

The present work investigates the hydrodynamic cavitation (HC) performance of vortex-diode based devices, which show early inception and superior cavitational performance compared to conventional devices. The study provides novel data on the cavitational efficiency at different operating pressures for two sizes of cavitation devices, addressing a gap in the literature. Using coumarin as a chemical dosimeter in acidic conditions, the study tracked the formation of 7-hydroxycoumarin (7OHC), a hydroxylation product of coumarin, to evaluate cavitational performance. Optimization of solution pH and initial concentration led to selecting pH 3 and a 15 ppm concentration for subsequent experiments with two vortex-diode devices of 12 mm (D12) and 6 mm (D6) diameters. These devices were tested under various pressure conditions. The formation of 7OHC was analyzed in relation to process time, number of passes, and a characteristic number of passes (n*) – which correlates device dimensions with operating velocity. The results indicated that the D6 device outperformed the D12 in terms of efficiency at inlet pressures ranging from 100 to 400 kPag. Analysis of 7OHC formation trends with respect to n* revealed that while there were variations within different pressures for a given device, the performance was comparable across different scales. By keeping a constant n* across varying pressures (P1 = 100 to 400 kPag and P2 = 0 to 300 kPag), the study observed comparable 7OHC formation across different operating conditions and scales. This data is vital for selecting suitable scales and conditions for HC devices and for validating multi-scale models in this field.

Hybrid bimetallic phosphonates as cathode materials for miniaturized in-plane asymmetric supercapacitor device

The utilization of wearable electronic devices facilitates the development of smart and flexible technology as a superior energy storage device that minimizes the dimension of wearable devices. The simple vacuum filtration method was employed to fabricate the micro-supercapacitor device (MSC) using the as-synthesized bimetallic nickel cobalt phosphonate (NiCoNPO) on the PVDF membrane as substrate. Novel microporous bimetallic metal phosphonates (NiCoNPO, Ni2CoNPO, NiCo2NPO) have been synthesized in a hydrothermal reaction condition by varying the molar ratio (Ni1:Co1; Ni2:Co1; Ni1:Co2) of metal sources without any employment of templating agent. Among these, NiCoNPO exhibits the remarkable specific capacitance of 2308 F g−1 at 1 mV s−1 and long-term cyclic stability up to the 5000th cycle with 99.6 % capacity retention in the three-electrode system. In addition, the electrode material demonstrates an exceptional capacitance of 574 F g−1 with stability (87.6 % retention) in a two-electrode system. Also, it displays excellent performance as a flexible MSC device with an areal capacitance of 123.5 mF cm−2. Notably, the MSC demonstrates long-term stability up to the 5000th cycle with a capacity retention of 85.6 %, suggesting the electrode material has excellent mechanical flexibility and superior electrochemical performance.

Tweaking the Performance of Dielectric Modulated Junctionless Double Gate Metal Oxide Field Effect Transistor-Based Label-Free Biosensor

In this study, we have explored the characteristics of a dielectric-modulated, junctionless (JL) double gate (DG) metal oxide field-effect transistor (MOSFET) featuring a misaligned cavity. Our investigation primarily revolves around proposing optimized device dimensions by examining the influence of varying the height and length of the cavity on the device’s sensitivity. We have delved into the variation of sensitivity parameters, including threshold voltage, ON current, ON-OFF current ratio, and transconductance. Furthermore, our research delves into the effects of both charged and neutral biomolecules on the DC characteristics of the proposed biosensor. We have scrutinized the placement and fill-factor variations of biomolecules within the cavity region, elucidating their impact on sensitivity. Notably, we observed that a 100% filled cavity yields the highest sensitivity. Additionally, this work encompasses a comprehensive exploration of the practical biosensing mechanism tailored for detecting Streptavidin. Based on the ON-OFF current ratio, a maximum selectivity factor of 2.38 (biotarget over bioreceptor) has been observed. Our extensive simulations, conducted using SILVACO ATLAS, rigorously investigate the effects we describe. Altogether, this study highlights the potential of misaligned-cavity JL-DG-MOSFET-based label-free biosensors as cost-effective and simplified analytical tools for biomolecule detection.

基于机器视觉的马铃薯幼苗破膜装置设计与试验

An automatic potato seedling film-breaking device based on machine vision was designed to reduce the labor intensity of potato film-breaking. The device mainly consists of a motion mechanism, a seedling recognition mechanism, a film-breaking mechanism, etc. Based on single-ridge and single-row potato planting agronomy, the whole structure and key component dimensions of the film-breaking device are determined, the YOLOv5s model is improved to build a potato seedling recognition system, and the film-breaking mechanism based on the parallel CoreXY structure is designed. Potato seedlings at the emerging stage are used as research objects for field film-breaking tests. The results show that the recognition rate of potato seedlings is 89.7%, the qualified rate of film-breaking is 83.5%, and the damage rate is 2.3%. This paper can provide technical support for the development of intelligent film-breaking equipment for potato seedlings.

Simulation and Analysis of Piezoresistive Microcantilever

Currently, most piezoresistive microcantilever sensors are configured with a dual-layer design that includes a piezoresistor integrated onto the upper surface of a microcantilever. The dual-layer design effectively enhances sensitivity and the piezoresistance effect. However, integrating the piezoresistor onto the microcantilever in the fabrication process necessitates additional steps, leading to extended manufacturing times and increased production costs. In this paper, the mechanical behavior of a single-layer piezoresistive microcantilever, namely displacement, stress, and strain, is investigated and analyzed using ANSYS Multiphysics. The contributing factors expected to affect the device's performance are its geometrical dimensions, and the materials used. Regarding the device dimensions, the length, thickness, and width of the cantilever were varied. It was found that the performance of the piezoresistive microcantilever can be improved by increasing the length and decreasing the thickness. The displacement of the microcantilevers increased by about 230%, from 75.76µm to 250.12µm, when the length was increased from 225µm to 350µm. The applied force ranged from 2uN to 12uN. Similarly, the stress and strain produced on the microcantilevers also increased by about 60.83% and 57.22%, respectively. From the material point of view, the microcantilever made with silicon always had the highest displacement value compared to silicon nitride, silicon dioxide, and polysilicon. This is due to the Young's modulus value, where materials with lower Young's modulus will have higher displacement and stress.

(Invited) Plasma-Enhanced Atomic Layer Etching for Metals and Dielectric Materials

The critical dimensions of semiconductor devices are continuously shrinking with 3D device structure and are approaching to nanometer scale. The demand for dimension control in angstrom level is drastically increasing also in etching processes. Atomic layer etching (ALE) processes are being actively studied and developed for various semiconductor, dielectric materials as well as metals. In this talk, various plasma-enhanced ALE (PEALE) processes will be discussed for isotropic and anisotropic patterning of metals and dielectric materials such as molibdenum, ruthenium, cobalt, titanium nitride, tantalum nitride, halfnium oxide, zirconium oxides.[1-7] Typical ALE processes consist of surface modification step and removal step. For the surface modification, various fluorination, chlorination and oxidation schemes are applied through fluorocarbon deposition, halogenation, oxidation with radicals generated plasmas. For the removal or etching step, various schemes were applied including ion-bomardment, heating, ligand volatilization, ligand exchange, and halogenation. The surface characteristics and requirements of plasma-enhanced ALE will be also discussed.1) K. Koh, Y. Kim, C.-K. Kim, H. Chae, J. Vac. Sci. Technol. A, 36(1), 10B106 (2017)2) Y. Cho, Y. Kim, S. Kim, H. Chae, J. Vac. Sci. Technol. A, 38(2), 022604 (2020)3) Y. Kim, S. Lee, Y. Cho, S. Kim, H. Chae, J. Vac. Sci. Technol. A, 38(2), 022606 (2020)4) D. Shim, J. Kim, Y. Kim, H. Chae, J. Vac. Sci. Technol. B., 40(2) 022208 (2022)5) Y. Lee, Y. Kim, J. Son, H. Chae, J. Vac. Sci. Technol. A., 40(2) 022602 (2022)6) J. Kim, D. Shim, Y. Kim, H. Chae, J. Vac. Sci. Technol. A., 40(3) 032603 (2022)7) Y. Kim, S. Chae, H. Ha, H. Lee, S. Lee, H. Chae, Appl. Surf. Sci. 619, 156751 (2023)

(Keynote) ALD Challenges and Opportunities in Light of Future Trends in Si-Based Nanoelectronics

To enable CMOS transistor density scaling following Moore’s Law, device architectures transitioned in the past decade from the historical 2D planar transistor to FINFET. The next innovation touted for the 3nm node is a 3D stacked gate-all-around architecture in combination with a backside power delivery network. For further scaling, stacking nmos and pmos, the so-called complementary-FET (CFET) design, is envisaged to happen in 2030. The shrinking device dimensions of the interconnects require also new metallization schemes to tackle the RC challenge, such as Cu replacements materials in a direct metal etch integration scheme. Beyond the CFET era, one envisages the introduction of 2D-grown channel materials that will pave the way for further scaling. A broad variety of complementary deposition techniques will be needed to enable the above-mentioned novelties; among them ALD that will play a crucial role.A similar trend towards stacking functional cells can be observed in various memories, such as the emerging memories that aim to bridge the gap between DRAM and NAND, thereby enabling fast data storage and retreival for real-time processing in connected devices at low cost. These memories are based on phase change, filamentary, magnetic, or ferroelectric mechanisms and often use multi-element materials. They have been extensively explored in 2D capacitor or transistor based devices, but for further density scaling 3D device designs are needed where a conformal deposition technique such as ALD is required. Cell scaling challenges also hold for the traditional DRAM which lead to exploring 3DDRAM integration routes. One viable pathway for scaling implies the replacement of the typical Si-channel based transistor by a deposited semiconductor oxide channel. Ultimate 3DDRAM implementation would require a conformal deposition of that channel.In this presentation, we will discuss the opportunities and challenges of ALD in a 3D-evolving device landscape where new materials will play a key role.