Active Region Of Device Research Articles

Double-metal waveguide terahertz difference-frequency generation quantum cascade lasers with surface grating outcouplers

We report terahertz quantum cascade laser (QCL) sources based on intra-cavity difference-frequency generation processed into double-metal waveguides with surface-grating outcouplers. This configuration enables high confinement of the terahertz mode in the device active region and efficient surface extraction of terahertz radiation along the entire length of the waveguide. The devices operate at room temperature at 1.9 THz and produce over 110 μW of peak power output with the mid-infrared-to-terahertz conversion of 150 μW/W2. The results represent at least a factor of 2 improvement in the performance compared to the best Cherenkov difference-frequency generation QCL devices operating below 2 THz.

Strategies for Thinning Graded Buffer Regions in Metamorphic Solar Cells and Performance Tradeoffs

Compositionally graded buffers (CGBs) have enabled the development of inverted metamorphic multijunction solar cells that contain three or more junctions and exhibit record efficiencies. Typically, the CGB is grown thick with a constant strain grading rate, because that is the most straightforward way to minimize the threading dislocation density (TDD) in device active regions. The CGB growth represents a significant expense, in terms of materials consumption and capital cost, however, hampering the economic viability of metamorphic devices. This work explores strategies for thinning Ga1- x In x P CGBs from GaAs to InP while minimizing performance loss, as evaluated by the open-circuit voltage ( $V_{{\text{OC}}}$ ) of ∼0.74 eV Ga0.47In0.53 As solar cells. Using the Ga1- x In x P CGB as a model, we demonstrate that slower grading is necessary in certain regions of the grade where dislocation nucleation rates are higher. Grading must be more gradual in these regions to suppress TDD. Grading rates can be increased in noncritical areas where dislocation nucleation is lower, permitting a thinner buffer. We demonstrate the relationship between V OC and TDD, establishing tradeoffs between thickness and performance. Through careful design, we demonstrate a CGB with a 40% thickness reduction (2 μm) achieved with a $V_{{\text{OC}}}$ decrease of only 7.5% (25 mV).

An improved design approach for thin film solar cells

In this paper an improved design for thin film solar cells is proposed to enhance conversion efficiency. This proposed structure includes two pairs of additional contact to the reversed bias of absorber and buffer layers, directly. The purpose of additional electrodes is to control the carrier distribution in the active region of device. This idea has been implemented on the fabricated Copper indium gallium selenide solar cell with the record efficiency of 22%. The simulations show an improvement of 2% in the conversion efficiency is obtained by direct application of reverse biasing on the absorber and buffer layer. The increase of short circuit current more than 3 mA/cm2 is responsible for the improved performance. The open circuit voltage and fill factor of cell can also be increased by the controlling reverse bias.

Effect of quantum confinement on lifetime of anharmonic decay of optical phonons in semiconductor nanostructures

The anharmonic decay of phonons underlies many important effects in semiconductors, e.g. hotspot formation, phonon bottleneck and thermal resistivity. In this article, we evaluate the effect of quantum confinement on the anharmonic decay transition probability in a cubic isotropic material. This article focuses on the anharmonic decay of longitudinal optical phonons, generated from hot electrons, are directly related to formation of hotspots in the active region of semiconductor devices. The confinement effect has been realized in double interface heterostructure quantum well (DHSQW) (e.g. AlAs/GaAs/AlAs) and free-standing quantum well (FSQW) (e.g. GaAs) structures as the confined phonon modes have different properties inside the structures. The longitudinal–optical phonon decay rate is reduced for the case of a DHSQW compared to bulk material and for a FSQW the decay rate has a strong dependence on wavevector value of the three phonons involved.

(Invited) Proximity Gettering Design of Hydrocarbon Molecular Ion Implanted Silicon Wafers Using Direct Bonding Technique for Advanced CMOS Image Sensors: A Review

Complementary metal oxide semiconductor (CMOS) image sensors have become widely used ubiquitous devices such as smart phone and personal computer type tablets. Consumer markets strongly demands more high sensitivity imaging and more high speed image data processing for achieving advanced CMOS image sensor fabrication. However, there are some serious improvement technical issues in CMOS image sensor fabrication process. Extremely important technical issue is metallic impurity contaminated device active region during device fabrication process such as high temperature rapid thermal annealing, dry etching and plasma heat treatment. Metallic impurities formed deep energy level defects in the silicon band-gap. Thus, these deep energy level defects strongly affects electrical device characteristic such as pn-junction leakage current, recombination lifetime and gate oxide breakdown voltage. Another technical issue is oxygen impurity out-diffused to the device active region from a Czochralski (CZ) grown silicon substrate during device heat process. Oxygen impurity formed oxygen related deep energy level defects in the device active region of photo-diode space charge region and transfer transistor gate channel region. These oxygen related defects strongly influenced on electrical device performance such as image lag. Therefore, in recent years, CMOS image sensor manufacturers have strongly demanded silicon wafers with the highest metal and oxygen impurities gettering capability during CMOS device processes. In response, we have developed a novel gettering wafer production concept using a hydrocarbon molecular ion implantation technique for advanced CMOS image sensors [1][2][3]. This technique can implant a silicon wafer surface simultaneously with carbon and hydrogen elements that form the projection range using a hydrocarbon compound molecular gas source. In our previous study, it was found that a hydrocarbon molecular ion implanted silicon wafer had three unique characteristics for high performance of advanced CMOS image sensors. First, a hydrocarbon molecular ion projection range has high gettering capability of metallic impurities [1][2][4]. Second, this projection range also has a diffusion barrier effect for oxygen impurities out-diffusing to the device active region from a CZ grown silicon wafer substrate [5]. Third, it is expected that diffusing hydrogen to the device active region from the hydrogen of hydrocarbon molecular ions gettered in the projection range during the device fabrication process will have a passivation effect on unreconstructed surface dangling bonds and Si/SiO2 interface state densities such as local oxidation of silicon or shallow trench isolation [6][7]. Moreover, we achieved more improvement for gettering capability of hydrocarbon molecular ion implanted silicon wafer which formed epitaxial layer without epitaxial growth process using room temperature direct bonding technique. In this presentation, we demonstrate that a hydrocarbon molecular ion implanted silicon wafers using room temperature direct bonding technique has high gettering capability characteristics for transition metal and light element impurities such as oxygen, and hydrogen during the CMOS image sensor fabrication process.

(Invited) Integration of Diamond with GaN for Thermal Management in High Power Applications

The development of compound semiconductor, wide bandgap electronics based on GaN is poised to impact future rf and advanced power electronic switches. The performance and reliability of these devices is impacted by heat dissipation, which is necessary in order to maintain reasonable device temperatures. Diamond is considered to be a suitable material to promote heat transfer away from the active regions of devices, and recently, several techniques have been developed to integrate diamond with semiconductor materials to achieve effective heat dissipation. We address the properties of polycrystalline diamond, both in thin film and bulk form, to better understand how the polycrystalline nature of diamond impacts thermal conductivity. The deposition of diamond onto, for example, GaN requires the inclusion of interfacial layers; the stability of these layers plays a large role in their effectiveness to protect the semiconductor from the deposition byproducts and to facilitate heat transfer from the GaN to the diamond layer. Novel surface engineering techniques also impact thermal transport across interfaces. We employed transmission electron microscopy imaging and electron energy loss spectroscopy, electron backscattered diffraction (SEM) and precession electron diffraction(TEM), high resolution x-ray scattering, combined with thermal transport measurements to address these issues.

(Invited) Integration of Diamond with GaN for Thermal Management in High Power Applications

Heat dissipation is an important consideration for electronic devices used in high power applications. Diamond is considered to be a suitable material to promote heat transfer away from the active regions of devices, and recently, several techniques have been developed to integrate diamond with GaN layers to achieve effective heat dissipation. Since the deposition of diamond onto GaN requires the inclusion of interfacial layers, the stability of these layers plays a large role in their effectiveness to protect the GaN substrate. In this work, samples with SiN or no interfacial layer have been analyzed before and after diamond deposition to study the influence of the by-products of diamond chemical vapor deposition on the interfacial layer. Characterization of the interfacial layer was performed using transmission electron microscopy and x-ray reflectivity. For example, a ~ 6.3 nm SiN layer deposited on a GaN structure prior to diamond deposition was reduced to 2 nm after deposition. The layer remained continuous and offered protection to the underlying GaN substrate. The interface of samples without an interfacial layer were much rougher than those with interfacial layers. In addition, the controlled removal of the dielectric layer at the start of the diamond deposition reduces the contribution of these low thermal conductivity layers to thermal resistance.

(Invited) Proximity Gettering Design of Hydrocarbon Molecular Ion Implanted Silicon Wafers Using Direct Bonding Technique for Advanced CMOS Image Sensors: A Review

We developed high gettering capability silicon wafers for advanced CMOS image sensors using hydrocarbon molecular ion implantation and surface activated direct wafer bonding (SAB). We found that this novel wafer has three unique characteristics for the improvement of CMOS image sensor device performance. The first is metallic impurity gettering capability in the hydrocarbon ion implantation projection range during CMOS device fabrication. The second is the oxygen out-diffusion barrier effect; this wafer can control out-diffusion to the device active region from the CZ grown silicon substrate during CMOS device heat treatment. The third is the hydrogen passivation effect; hydrogen passivates to the Si/SiO2 gate oxide interface state defects which out-diffuse to the device active region from the hydrocarbon ion implantation projection range during the CMOS device fabrication. Moreover, we demonstrated that this novel wafer can improve the pn-junction leakage current under the actual device fabrication.

Device physics of van der Waals heterojunction solar cells

Heterostructures based on atomically thin semiconductors are considered a promising emerging technology for the realization of ultrathin and ultralight photovoltaic solar cells on flexible substrates. Much progress has been made in recent years on a technological level, but a clear picture of the physical processes that govern the photovoltaic response remains elusive. Here, we present a device model that is able to fully reproduce the current–voltage characteristics of type-II van der Waals heterojunctions under optical illumination, including some peculiar behaviors such as exceedingly high ideality factors or bias-dependent photocurrents. While we find the spatial charge transfer across the junction to be very efficient, we also find a considerable accumulation of photogenerated carriers in the active device region due to poor electrical transport properties, giving rise to significant carrier recombination losses. Our results are important to optimize future device architectures and increase power conversion efficiencies of atomically thin solar cells.

Demonstration of AlN Schottky Barrier Diodes With Blocking Voltage Over 1 kV

This letter reports the first demonstration of 1-kV-class AlN Schottky barrier diodes on sapphire substrates by metal organic chemical vapor deposition. The device structure mimics the silicon-on-insulator (SOI) technology, consisting of thin $n$ -AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the devices show outstanding performances with a low turn-ON voltage of 1.2 V, a high ON/OFF ratio of $\sim 10^{5}$ , a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. The devices also exhibit excellent thermal stability over 500 K owing to the ultra-wide bandgap of AlN. The breakdown voltage of the devices can be further improved by employing field plate, edge termination technologies, and optimizing the SOI-like device structure. This letter presents a cost-effective route to high performance AlN-based Schottky barrier diodes for high-power, high-voltage, and high-temperature applications.

Type-I band alignment at MoS2/In0.15Al0.85N lattice matched heterojunction and realization of MoS2 quantum well

The valence and conduction band offsets (VBO and CBO) at the semiconductor heterojunction are crucial parameters to design the active region of contemporary electronic and optoelectronic devices. In this report, to study the band alignment parameters at the In0.15Al0.85N/MoS2 lattice matched heterointerface, large area MoS2 single layers are chemical vapor deposited on molecular beam epitaxial grown In0.15Al0.85N films and vice versa. We grew InAlN having an in-plane lattice parameter closely matching with that of MoS2. We confirm that the grown MoS2 is a single layer from optical and structural analyses using micro-Raman spectroscopy and scanning transmission electron microscopy. The band offset parameters VBO and CBO at the In0.15Al0.85N/MoS2 heterojunction are determined to be 2.08 ± 0.15 and 0.60 ± 0.15 eV, respectively, with type-I band alignment using high-resolution x-ray photoelectron spectroscopy in conjunction with ultraviolet photoelectron spectroscopy. Furthermore, we design a MoS2 quantum well structure by growing an In0.15Al0.85N layer on MoS2/In0.15Al0.85N type-I heterostructure. By reducing the nitrogen plasma power and flow rate for the overgrown In0.15Al0.85N layers, we achieve unaltered structural properties and a reasonable preservation of photoluminescence intensity with a peak width of 70 meV for MoS2 quantum well (QW). The investigation provides a pathway towards realizing large area, air-stable, lattice matched, and eventual high efficiency In0.15Al0.85N/MoS2/In0.15Al0.85N QW-based light emitting devices.

(Invited) Achieving Vertical Trench-Gate GaN MOSFETs via Process Optimization

Gallium nitride is a strong candidate material for advanced power electronics that exceed the capabilities of current Si and SiC technologies. The ideal device structure for GaN power switches is the vertical metal-oxide-semiconductor field effect transistor (MOSFET). Current vertical GaN MOSFETs have not reached theoretical performance limits. Optimization of these devices is required to improve their performance, particularly with respect to the dielectric/semiconductor interface along the device active regions, and processing used to fabricate the vertical channel regions. We have studied two atomic layer deposition precursor systems for ZrO2 dielectrics on both as-grown and plasma-etched c-plane GaN. Piranha etching of GaN surfaces before ALD improved the capacitance-voltage response of the deposited ZrO2. 5-10 µm deep trenches in GaN substrates have also been fabricated, to allow more detailed study of the trench sidewalls and dielectric interfaces on the etched surfaces before and after hydroxide-based wet etching.

Nano-structured metal-semiconductor-metal photodetector for sensor network systems

The advanced and smart ways to produce complex nano-structures have incorporated new capabilities in various aspects of science and technology where structures on nano-meter scales are desirable including high-speed communication and sensor networks, and future biomedical sensors and detectors. In recent years, there has been a growing interest towards the miniaturization of optical and electrical components with faster and more efficient performance. The development of nano-materials and nano-structures design provides great opportunity for building multifunctional sensing elements which are smaller and more efficiently incorporated. Furthermore they have other useful characteristics like reduced production cost and minimized power consumption. Wireless sensor network systems have been identified as one of the most important technologies for the 21st century (Chong et. al., 2003). It can be deduced from its name that sensor network systems are composed of several sensor nodes, where each component is responsible for a function in the whole system, where it can consist of different kinds of sensors such as, thermal, visual, biomedical, infrared, acoustics, etc. Recent wireless communication system development requires a concurrent speedy advancement of sensors characteristics as well as the system performance. Therefore, it is very important to make the progress in sensors design with tiny dimensions, suitable for communication over a sensor network system with specified purposes such as, monitoring different parameters, namely humidity, temperature, light in household, cities, and different environments (Ian-Akyildiz et al., 2002). The main focus of this review is to design and model an optimized plasmonics-based metal-semiconductor-metal photodetectors (MSM-PDs) with sub-wavelength architectures that is useful for high-speed optical communication systems and sensor network systems. Nano-structures designed on top of the electrodes trigger surface plasmon polaritons (SPPs) excitation and enable routing and manipulation of the light to be eventually trapped into the device active region.

Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion‐implantation technique: A review

A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out‐diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen‐related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn‐junction leakage current, and image lag characteristics. The new technique enables the formation of high‐gettering‐capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors.

Defect Coupling and Sub-Angstrom Structural Distortions in W1-xMoxS2 Monolayers.

Two-dimensional materials offer a remarkably rich materials platform to study the origin of different material behaviors at the atomic level, and doping provides a key means of tailoring such materials' functional properties. The local atomic structure around such dopants can be critically important in determining the material's behavior as it could modulate scattering, catalytic activity, electronic and magnetic properties, and so forth. Here, using aberration-corrected scanning transmission electron microscopy (STEM) with sub-Ångstrom resolution in conjunction with density functional theory calculations, we demonstrate a strong coupling between Mo dopants and two types of defects in WS2 monolayers: sulfur monovacancies and grain boundaries. Although Mo does occupy a transition metal lattice site, it is not an ideal substitutional dopant: ∼80% of the S vacancies identified by STEM colocalize with Mo dopants, an affinity that appears to be enhanced by symmetry breaking of a partially occupied midgap defect state. Although a Mo dopant by itself does not considerably distort the WS2 lattice, it induces substantial lattice deformation by apparently facilitating the charging of a sulfur monovacancy paired with it, which is consistent with the results of first-principles calculations. This coupling of foreign substitutional dopants with vacancies could potentially be exploited to control the distribution and location of chalcogenide vacancies within transition metal dichalcogenides (TMD), by segregating vacancies into regions of high Mo concentration that are purposely placed away from active regions of TMD-based devices.

Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices

This work pursues a multi-scale modeling approach to combine interconnect and device level simulation in order to study the effects of carrier self-heating and thermal transport on device performance. More specifically, this work will focus on power consumption and heat dissipation in silicon CMOS technology. As device dimensions decrease to the nanometer scale, current density in the device active regions and the circuit interconnects increases [4]. This increase in current density leads to substantial increases in operating temperatures in critical regions of nano-scale electronic devices. We have already shown these effects in n-channel MOSFETs [2], and will continue to explore how this phenomenon affects p-channel MOSFETs and CMOS circuits. This paper presents the methodology used for the study, multi-scale results from the n-channel MOSFET simulations, and preliminary results from the device level p-channel MOSFET simulation. The modeling approach combines an electro-thermal device simulation with a thermal transport solver at the circuit level. The electrical simulation solves Poisson's equations self-consistently coupled with an ensemble Monte Carlo to determine internal electric fields and model electron and hole transport in the device [3]. The thermal simulation solves the energy balance equations for acoustic and optical phonons and uses the phonon energy to determine the lattice temperature [5]. The electro-thermal solver couples these two processes by introducing temperature dependent scattering to the carrier transport solver. Thermal transport can be modeled in a variety of ways: phonon Monte Carlo simulations are necessary for modeling extreme nano-scale and hot-carrier devices, energy balance modeling is used in this study to model thermal transport at the device level, and the Joule heating method commonly used in commercial device simulators is used in this study to model thermal transport at the interconnect level. The thermal modeling in the device and the interconnects is coupled using the device structure itself as an interface: the electro-thermal simulator provides Joule heating terms throughout the device to be used in the Joule heating simulator which in turn gives the temperature profile in the interconnects to be used as a boundary condition in the electro-thermal solver. These simulations are repeated in a self-consistent loop until convergence is achieved [2]. This modeling approach has been successfully applied to n-channel MOSFET devices and the results have been confirmed using a novel experimental approach. Two identical MOSEFTs in either common source or common drain configuration can be biased such that one device is in saturation and one device is in cut-off or sub-threshold region. The device in saturation heats up and the device in sub-threshold is used as a sensor; the temperature in the sensor can be determined using the subthreshold slope [2]. Confirming the simulation results with experimental results for the temperature in the subthreshold device substantiates the accuracy of the methodology for determining the temperature throughout the device [2]. This methodology, now verified by comparison with experimental results for n-channel MOSFETS, will be applied to the study of CMOS circuits.

High photoresponse in room temperature quantum cascade detector based on coupled quantum well design

We report high photoresponse measured in a room temperature quantum cascade detector (QCD) based on a coupled quantum well design that operates with a peak response wavelength of 5.4 μm. The coupled quantum well design is expected to produce higher photocurrents when compared with device active regions that use a combination of simple quantum wells. The coupled quantum well QCD demonstrated high responsivity of 22 mA/W at room temperature with a commonly used 45° wedge-based light coupling configuration. Application of a waveguide configuration to the proposed QCD yielded an elevated responsivity of ∼130 mA/W and a specific detectivity (D*) of 1.1 × 108 cm W−1 Hz1/2 at room temperature.

Numerical characterization of InP-based quantum dot semiconductor optical amplifier.

This paper is devoted to the development of a steady-state behavior of a quantum dot-semiconductor optical amplifier (QD-SOA). The investigated performance characteristics cover a wide range that includes material gain coefficient, spatial distribution of the occupation probabilities, fiber to fiber gain, gain spectrum as a function of the bias current, relaxation time, and capture time. A set of traveling-wave equations is used to model the signal and spontaneous photons along the device active region. The obtained results indicate a high gain that reaches 34 dB for an InAs/InGaAsP/InP-based QD-SOA, with a corresponding device length of 4 mm. The obtained signal-to-noise ratio is larger than 75 dB for all input powers without using an output filter.

Proximity gettering of C3H5 carbon cluster ion-implanted silicon wafers for CMOS image sensors: Gettering effects of transition metal, oxygen, and hydrogen impurities

A new technique is described for manufacturing silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication. It is demonstrated that this technique can implant wafers simultaneously with carbon and hydrogen elements that form the projection range by using hydrocarbon compounds. Furthermore, these wafers can getter oxygen impurities out-diffused from the silicon substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as dark current and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly reduce dark current in advanced CMOS image sensors.

High Light Extraction Efficiency AlGaInP LEDs With Proton Implanted Current Blocking Layer

Improving light extraction efficiency is the key issue for light-emitting diodes (LEDs). Nowadays, a vertical structure design dominates LEDs. However, the light from the active region just below the p-electrode is severely blocked by the metal contact. In this letter, we use proton implantation with a depth all the way to the active region to turn the part beneath the p-pad insulating, which constitutes the most-effective-ever current blocking method. Earlier particle implantation studies never reached the device active region. Our experimental results show that the H+-implanted LEDs improve the light output power by 75% compared with non-implanted counterparts and the light intensity increases by 64.48%. By virtue of indium tin oxide current spreading film, the increase in working voltage is negligible. Analyzing the reverse leakage current, the side effect associated with the implantation is limited to an acceptable range. Numerical simulation is performed to support the experiment. Our results represent a new and simple method for solving the light blocking problem in vertical LEDs, without introducing the seemingly existing severe implantation damage to the device structure.