Deterministic Test Research Articles

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories. The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high. Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time.

Estimating the effect of monopsony power on elasticity estimates

ABSTRACTLove and Shumway (1994) developed a nonparametric deterministic test for monopsony market power using a normalized quadratic restricted cost function with one input for which the firm has potential market power. This research examines monopsony power using Lau’s Hessian identity relationships based on the empirical properties of duality theory. Lau’s Hessian identity shows the Hessian matrices are equal under pure competition using an unrestricted profit function, restricted profit function and production function approach. We examine how market power changes in the monopsony case using Lau’s Hessian identity relationships. Results show that there is a difference between the unrestricted and restricted profit function results under monopsony power. The important implication is that if an input or output is potentially in a market subject to market power, that input or output should be modelled as a fixed input or output to correctly recover the underlying technology.

SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment

This paper presents a new SOC test compression scheme in Embedded Deterministic Test (EDT) compression environment. Compressed test data is brought over the TAM from the tester to the cores in SOC and decompressed in the cores. The proposed scheme allows cores tested at the same time to share some test channels. By sharing free variables in these channels across test cubes of different cores decompressed at the same time, high encoding efficiency is achieved. Moreover, no excess control data is required in this scheme. The ability to reuse excess free variables eliminates the need for high precision in matching the number of test channels with the number of care bits for every core. Experimental results obtained for some SOC designs illustrate effectiveness of the proposed test application scheme.

Active Hypothesis Testing for Anomaly Detection

The problem of detecting a single anomalous process among a finite number M of processes is considered. At each time, a subset of the processes can be observed, and the observations from each chosen process follow two different distributions, depending on whether the process is normal or abnormal. The objective is a sequential search strategy that minimizes the expected detection time subject to an error probability constraint. This problem can be considered as a special case of active hypothesis testing first considered by Chernoff where a randomized strategy, referred to as the Chernoff test, was proposed and shown to be asymptotically (as the error probability approaches zero) optimal. For the special case considered in this paper, we show that a simple deterministic test achieves asymptotic optimality and offers better performance in the finite regime. We further extend the problem to the case where multiple anomalous processes are present. In particular, we examine the case where only an upper bound on the number of anomalous processes is known.

Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

Some remarks on primality proving and elliptic curves

We give an overview of a method for using elliptic curves with complex multiplication to give efficient deterministic polynomial time primality tests for the integers in sequences of a special form. This technique has been used to find the largest proven primes $N$ for which there was no known significant partial factorization of $N-1$ or $N+1$.

Development and validation of a dynamic metamodel based on stochastic radial basis functions and uncertainty quantification

A dynamic radial basis function (DRBF) metamodel is derived and validated, based on stochastic RBF and uncertainty quantification (UQ). A metric for assessing metamodel efficiency is developed and used. The validation includes comparisons with a dynamic implementation of Kriging (DKG) and static metamodels for both deterministic test functions (with dimensionality ranging from two to six) and industrial UQ problems with analytical and numerical benchmarks, respectively. DRBF extends standard RBF using stochastic kernel functions defined by an uncertain tuning parameter whose distribution is arbitrary and whose effects on the prediction are determined using UQ methods. Auto-tuning based on curvature, adaptive sampling based on prediction uncertainty, parallel infill, and multiple response criteria are used. Industrial problems are two UQ applications in ship hydrodynamics using high-fidelity computational fluid dynamics for the high-speed Delft catamaran with stochastic operating and environmental conditions: (1) calm water resistance, sinkage and trim with variable Froude number; and (2) mean value and root mean square of resistance and heave and pitch motions with variable regular head wave. The number of high-fidelity evaluations required to achieve prescribed error levels is considered as the efficiency metric, focusing on fitting accuracy and UQ variables. DKG is found more efficient for fitting low-dimensional test functions and one-dimensional UQ, whereas DRBF has a greater efficiency for fitting higher-dimensional test functions and two-dimensional UQ.

Scan power-aware deterministic test scheme using a low-transition linear decompressor

Growing test data volume and excessive testing power are both serious challenges in the testing of very large-scale integrated circuits. This article presents a scan power-aware deterministic test method based on a new linear decompressor which is composed of a traditional linear decompressor, k-input AND gates and T flip-flops. This decompression architecture can generate the low-transition deterministic test set for a circuit under test. When applying the test patterns generated by the linear decompressor, only a few transitions occur in the scan chains, and hence the switching activity during testing decreases significantly. Entire test flow compatible with the design is also presented. Experimental results on several large International Symposium on Circuits and Systems’89 and International Test Conference’99 benchmark circuits demonstrate that the proposed methodology can reduce test power significantly while providing a high compression ratio with limited hardware overhead.

Primality testing for beginners

How can you tell whether a number is prime? What if the number has hundreds or thousands of digits? This question may seem abstract or irrelevant, but in fact, primality tests are performed every time we make a secure online transaction. In 2002, Agrawal, Kayal, and Saxena answered a long-standing open question in this context by presenting a deterministic test (the AKS algorithm) with polynomial running time that checks whether a number is prime or not. What is more, their methods are essentially elementary, providing us with a unique opportunity to give a complete explanation of a current mathematical breakthrough to a wide audience. Rempe-Gillen and Waldecker introduce the aspects of number theory, algorithm theory, and cryptography that are relevant for the AKS algorithm and explain in detail why and how this test works. This book is specifically designed to make the reader familiar with the background that is necessary to appreciate the AKS algorithm and begins at a level that is suitable for secondary school students, teachers, and interested amateurs. Throughout the book, the reader becomes involved in the topic by means of numerous exercises.

Area-efficient high-coverage LBIST

Logic Built-In Self Test (LBIST) is a popular technique for applications requiring in-field testing of digital circuits. LBIST incorporates test generation and response-capture on-chip. It requires no interaction with a large, expensive tester. LBIST offers test time reduction due to at-speed test pattern application, makes possible test data re-usability at many levels, and enables test-ready IP. However, the traditional pseudo-random pattern-based LBIST often has a low test coverage. This paper presents a new method for on-chip generation of deterministic test patterns based on registers with non-linear update. Our experimental results on 7 real designs show that the presented approach can achieve a higher stuck-at coverage than the test point insertion with less area overhead. We also show that registers with non-linear update are asymptotically smaller than memories required to store the same test patterns in a compressed form.

Sampling of Stochastic Operators

We develop sampling methodology aimed at determining stochastic operators that satisfy a support size restriction on the autocorrelation of the operators stochastic spreading function. The data that we use to reconstruct the operator (or, in some cases only the autocorrelation of the spreading function) is based on the response of the unknown operator to a known, deterministic test signal.

Test Time Reduction in EDT Bandwidth Management for SoC Designs

This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate selecting and laying out automatic test equipment channel injectors of every single core EDT-based decompressor as well as appropriate bandwidth management of the entire test procedure combined with new control data optimization techniques. The efficacy of the proposed scheme is validated through experiments on several industrial SoC designs and is reported herein.

An efficient deterministic test for Kloosterman sum zeros

We propose a simple deterministic test for deciding whether or not an element a ∈ F×2n or F×3n is a zero of the corresponding Kloosterman sum over these fields, and rigorously analyse its runtime. The test seems to have been overlooked in the literature. The expected cost of the test for binary fields is a single point-halving on an associated elliptic curve, while for ternary fields the expected cost is one-half of a point-thirding on an associated elliptic curve. For binary fields of practical interest, this represents an O(n) speedup over the previous fastest test. By repeatedly invoking the test on random elements of F×2n we obtain the most efficient probabilistic method to date to find nontrivial Kloosterman sum zeros. The analysis depends on the distribution of Sylow p-subgroups in the two families of associated elliptic curves, which we ascertain using a theorem due to Howe.

Optimising pseudo‐random built‐in self‐testing of fully synchronous as well as multisynchronous networks‐on‐chip

Most built-in self-test architectures use pseudo-random test pattern generators. However, whenever this technique has been applied to on-chip interconnection networks, overly large testing latencies have been reported. On the other hand, alternative approaches either suffer from large area penalties (like scan-based testing or the use of deterministic test patterns) or poor fault coverage in the control path (functional testing). Moreover, the recent proliferation of clock domains on a chip makes testing overly challenging. This manuscript presents the optimisation of a built-in self-testing framework based on pseudo-random test patterns to the microarchitecture of network-on-chip switches. As a result, fault coverage and testing latency approach those achievable with deterministic test patterns while materialising relevant area savings and enhanced flexibility. Finally, the authors implement the extension of the proposed testing methodology to multisynchronous systems, thus making it compliant with the relaxation of synchronisation assumptions in nanoscale designs.

THE COMPLEXITY OF COVERAGE

We study the problem of generating a test sequence that achieves maximal coverage for a reactive system under test. We formulate the problem as a repeated game between the tester and the system, where the system state space is partitioned according to some coverage criterion and the objective of the tester is to maximize the set of partitions (or coverage goals) visited during the game. We show the complexity of the maximal coverage problem for non-deterministic systems is PSPACE-complete, but is NP-complete for deterministic systems. For the special case of non-deterministic systems with a re-initializing “reset” action, which represent running a new test input on a re-initialized system, we show that the complexity is coNP-complete. Our proof technique for reset games uses randomized testing strategies that circumvent the exponentially large memory requirement of deterministic testing strategies. We also discuss the memory requirement for deterministic strategies and extensions of our results to other models, such as pushdown systems and timed systems.

Functional delay test generation approach using a software prototype of the circuit

The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the representation of the function of the circuit. The faults are considered on the inputs and on the outputs of the model only. The random input stimuli are generated and selected then according to the proposed approach. The experimental results demonstrate the superiority of the delay test stimuli generated at the functional level using the introduced approach against the transition test stimuli obtained at the gate level by deterministic test generator. The functional delay test generation approach especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.

Soft Computing Approach To Automatic Test Pattern Generation For Sequential Vlsi Circuit

Due to the constant development in the integrated circuits, the automatic test pattern generation problem become more vital for sequential vlsi circuits in these days. Also testing of integrating circuits and systems has become a difficult problem. In this paper we have discussed the problem of the automatic test sequence generation using particle swarm optimization(PSO) and technique for structure optimization of a deterministic test pattern generator using genetic algorithm(GA).

First Report of Bacterial Soft Rot of Potato Caused by Pectobacterium carotovorum subsp. carotovorum in Guangdong Province of China.

Potato (Solanum tuberosum L.) is a major crop in China, with 80.0 million tons being produced in 2010 on 3.3 million ha. Pectobacterium carotovorum subsp. carotovorum Jones 1901; Hauben et al. 1999 causes soft rot worldwide on a wide range of hosts including potato, carrot, and cabbage. During spring 2010, a soft rot with a foul smell was noted in stored potato tubers of different cultivars in the Guangdong Province. Symptoms on tubers appeared as tan, water-soaked areas with watery ooze. The rotted tissues were white to cream colored. Stems of infected plants with typical inky black symptoms could also be found in the fields prior to harvest. Three different potato fields were surveyed, and 13% of the plants had the symptoms. Twenty-seven samples (three symptomatic tubers per sample) were collected. Bacteria were successfully isolated from all diseased tissues on nutrient agar media supplemented with 5% sucrose and incubated at 26 ± 1°C for 36 h. After purification on tripticase soy agar media, four typical strains (7-3-1, 7-3-2, 8-3-1, and 8-3-2) were identified using the following deterministic tests: gram-negative rods, oxidase negative, facultatively anaerobic, able to degrade pectate, sensitive to erythromycin, negative for phosphatase, unable to produce acid from α-methyl-glucoside, and produced acid from trehalose. Biolog analysis (Ver 4.20.05, Hayward, CA) identified the strains as P. carotovorum subsp. carotovorum (SIM 0.808, 0.774, 0.782, and 0.786, respectively). The identity of strains 7-3-1 (GenBank Accession No. JX258132), 7-3-2 (JX258133), and 8-3-1 (JX196705) was confirmed by 16S rRNA gene sequencing (4), since they had 99% sequence identity with other P. carotovorum subsp. carotovorum strains (GenBank Accession Nos. JF926744 and JF926758) using BLASTn. Further genetic analysis of strain 8-3-1 was performed targeting informative housekeeping genes, i.e., acnA (GenBank Accession No. JX196704), gabA (JX196706), icdA (JX196707), mdh (JX196708), mtlD (JX196709), pgi (JX196710), and proA (JX196711) (2). These sequences from strain 8-3-1 were 99 to 100%, homologous to sequences of multiple strains of P. carotovorum subsp. carotovorum. Therefore, strain 8-3-1 grouped with P. carotovorum subsp. carotovorum on the phylogenetic trees (neighbor-joining method, 1,000 bootstrap values) of seven concatenated housekeeping genes when compared with 60 other strains, including Pectobacterium spp. and Dickeya spp. (3). Pathogenicity of four strains (7-3-1, 7-3-2, 8-3-1, and 8-3-2) was evaluated by depositing a bacterial suspension (106 CFU/ml) on the potato slices of cultivar 'Favorita' and incubating at 30 ± 1°C. Slices inoculated with just water served as non-inoculated checks. The strains caused soft rot within 72 h and the checks had no rot. Bacteria were reisolated from the slices and were shown to be identical to the original strains based on morphological, cultural, and biochemical tests. Although this pathogen has already been reported in northern China (1), to our knowledge, this is the first report of P. carotovorum subsp. carotovorum causing bacterial soft rot of potato in Guangdong Province of China.

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.

Idealized tropical cyclone simulations of intermediate complexity: A test case for AGCMs

The paper introduces a moist, deterministic test case of intermediate complexity for Atmospheric General Circulation Models (AGCMs). We suggest pairing an AGCM dynamical core with simple physical parameterizations to test the evolution of a single, idealized, initially weak vortex into a tropical cyclone. The initial conditions are based on an initial vortex seed that is in gradient‐wind and hydrostatic balance. The suggested “simple‐physics” package consists of parameterizations of bulk aerodynamic surface fluxes for moisture, sensible heat and momentum, boundary layer diffusion, and large‐scale condensation. Such a configuration includes the important driving mechanisms for tropical cyclones, and leads to a rapid intensification of the initial vortex over a forecast period of ten days. The simple‐physics test paradigm is not limited to tropical cyclones, and can be universally applied to other flow fields. The physical parameterizations are described in detail to foster model intercomparisons. The characteristics of the intermediate‐complexity test case are demonstrated with the help of four hydrostatic dynamical cores that are part of the Community Atmosphere Model version 5 (CAM 5) developed at the National Center for Atmospheric Research (NCAR). In particular, these are the Finite‐Volume, Spectral Element, and spectral transform Eulerian and semi‐Lagrangian dynamical cores that are coupled to the simple‐physics suite. The simulations show that despite the simplicity of the physics forcings the models develop the tropical cyclone at horizontal grid spacings of about 55 km and finer. The simple‐physics simulations reveal essential differences in the storm's structure and strength due to the choice of the dynamical core. Similar differences are also seen in complex full‐physics aqua‐planet experiments with CAM 5 which serve as a motivator for this work. The results suggest that differences in complex full‐physics simulations can be, at least partly, replicated in simplified model setups. The simplified experiments might therefore provide easier access to an improved physical understanding of how the dynamical core and moist physical parameterizations interact. It is concluded that the simple‐physics test case has the potential to close the gap between dry dynamical core assessments and full‐physics aqua‐planet experiments, and can shed light on the role of the dynamical core in the presence of moisture processes.