Gate Design Research Articles

Performance analysis of the photonic crystal–based X-OR gate for the terahertz applications

Abstract A key component of high-speed switching networks is an optical logic gate. This study presents the design and analysis of an all-optical XOR gate based on a two-dimensional photonic crystal (2D PC) structure, aiming to enhance high-speed switching in optical networks. The XOR gate, with two input and one output waveguide, is constructed on a hexagonal lattice, optimized for operation at a wavelength of 1,550 nm. The design is evaluated using the Finite Difference Time Domain (FDTD) approach, which simulates the optical performance of the structure. Key performance metrics, including the bit rate, contrast ratio, and delay time, are computed, showing that the proposed logic gate achieves a high contrast ratio of 30.35 dB and a minimal delay time of 0.4 ps. The results confirm the potential of this all-optical XOR gate for integration into high-speed optical circuits, offering low power consumption and high efficiency. This work demonstrates the feasibility of utilizing photonic crystal structures for high-performance optical logic gates in future communication systems. The simplicity of fabrication in a two-dimensional photonic crystal (2D-PC)-based all-optical logic gate can often be attributed to its simple design.

Design and numerical analysis of 4-inputs all-optical XOR gate in optical waveguides

Design and numerical analysis of 4-inputs all-optical XOR gate in optical waveguides

Design and realization of XOR, OR, and NAND light logic gates using GaAs heterostructure

This study introduces a novel structure based on a GaAs quantum well for implementing XOR, OR, and NAND light logic gates. This structure has unique advantages compared to classical p-n junction-based devices, including polarity-independent operation, radiation emission, and a more straightforward design. The suggested structure consists of two photoconductive devices and a logic gate device. When 850 nm light from the fiber optic cable illuminates the photoconductive device, the photoconductive device and the pulsed signal source are triggered simultaneously and supply the logic gate device, enabling it to perform the desired logic operation (XOR, OR, and NAND). Notably, at room temperature, the primary emission wavelength of these optical logic gate devices is 812 ± 1 nm. This design offers a compact, efficient, and versatile approach to light logic gates, with potential applications in optical computing and communication systems. Furthermore, the data transfer rate of these optical logic gates has been demonstrated to be comparable to that of electrical circuits currently used in technology.

Empirical Exploration of Optimal Gating System Design for Sand Casting Process

Purpose: This paper aims to analyse and optimise the gating system used in the sand casting process to produce drainage doors at Deepshikha Casting in Nagpur. It focuses on understanding how gate design impacts productivity and the quality of the cast, drawing attention to common defects and the role of gravity casting techniques. Design/Methodology/Approach: This paper discusses the present gating system of Deepshikha Casting in detail to identify defects, such as sand inclusions, blow holes, pinholes, gas holes, shrinkage, and misruns. The present gating ratio and system weight assessment are thus used to suggest changes in the design to improve the process efficiency and quality of the product. Findings: The research indicates that the existing gating system has an inappropriate gating ratio, resulting in a high rate of faults and reduced productivity. The system also weighs a lot, which deters efficiency. Improving the gating design reduces flaws, increases the quality of castings, and enhances molten metal flow. Research Limitation: The output of the present work is limited to Deepshikha Casting alone, which is used for drainage door casting. Further research must be conducted on different casting products and technologies for a broad application. Practical Implication: This sector of sand casting can benefit from optimising the gating system, maximising productivity and minimising casting defects, thus reducing costs and improving efficiency. Social Implication: The environment will also benefit from efficient casting because of reduced use of resources, reduced waste, and fewer consumables. Better procedures also translate to increased production of safer products. Originality/Value: This paper provides practical, applied solutions for optimising the gating system of sand casting. Its insights are particularly informative for a foundry working with fragile metals and using gravity casting.

Design of Multilayered XOR Gate Using Quantum Dot Cellular Automata

The rapid advancement of microelectronics technology necessitates the development of high-speed, low-power devices. Quantum Cellular Automaton (QCA) is emerging as a promising technology enabling logic circuits with exceptional operating speeds. The XOR gate is crucial in nanocomputing applications, such as nano-processors and nano-communication units, and requires innovative design approaches. This paper presents a novel design of an XOR gate using a multilayered layout methodology within the QCA framework. The circuit’s design and validation are performed using QCADesigner 2.0.3, while energy dissipation analysis is conducted with QCADesigner-E, resulting in an energy dissipation of 15 meV. Comprehensive parameter analysis, including cost functions, highlights the superiority of the proposed design. A comparative analysis with similar existing multilayered designs shows a 55% improvement in QCA-specific quantum cost. Notably, the proposed design eliminates the need for internal nodes within the layout, enhancing the methodology’s applicability to higher-order and more complex circuits.

Refined design of a DNA logic gate for implementing a DNA-based three-level circuit.

DNA computing circuits are favored by researchers because of their high density, high parallelism, and biocompatibility. However, compared with electronic circuits, current DNA circuits have significant errors in understanding the OFF state and logic "0". Nowadays, DNA circuits only have two input states: logic "0" and logic "1", where logic "0" also means the OFF state. Corresponding to an electronic circuit, it is more like an on-off switch than a logic circuit. To correct this conceptual confusion, we propose a three-level circuit. The circuit divides the input signal into three cases: "none", logic "0" and logic "1". In subsequent experiments, 34 input combinations of the primary AND gate, OR gate as well as secondary AND-OR and OR-AND cascade circuits were successfully implemented to perform the operation, which distinguished the OFF state and logic "0" correctly. Based on this, we successfully implemented a more complex voting operation with only 12 strands. We believe that our redefinition of the OFF state and logic "0" will promote tremendous developments in DNA computing circuits.

A Linear Mixed Effects Model for Evaluating Synthetic Gene Circuits.

A significant advancement in synthetic biology is the development of synthetic gene circuits with predictive Boolean logic. However, there is no universally accepted or applied statistical test to analyze the performance of these circuits. Many basic statistical tests fail to capture the predicted logic (OR, AND, etc.) and most studies neglect statistical analysis entirely. As synthetic gene circuits shift toward advanced applications, primarily in computing, biosensing, and human health, it is critical to standardize the statistical methods used to evaluate gate success. Here, we propose the application of a linear mixed effects model to analyze and quantify genetic Boolean logic gate performance. First, we analyzed 144 currently published Boolean logic gates for trends and used unsupervised machine learning (k-means clustering) to validate the statistical model. Next, we utilized the model to generate estimates for the fixed effect of the ON state, β, as a general descriptor of the Boolean nature of a circuit and used Monte Carlo simulations to recommend sample sizes for evaluating gate performance. Finally, we examined β as a holistic metric for circuit performance using a series of nested repressor OR gates with intentionally degraded performance. We observed a linear correlation between β and the predicted translation rate, highlighting the use of β for the forward design of new Boolean gates. In summary, we utilized a linear mixed effects model to describe synthetic gene circuits and determined that the fixed effect, β, is an appropriate descriptor of gate behavior that can be used to statistically evaluate performance.

Carrier Tunnelings on Ultrashort‐Gate Junction‐Less Field‐Effect Transistor Designs

This study discusses tunneling problems encountered when designing ultrashort‐gate junction‐less field‐effect transistors (FETs). Ultrathin‐body silicon‐on‐insulator (UTB‐SOI) FETs are suitable for nano‐length gate designs owing to the augmented bandgap at channel regions. However, a comprehensive understanding of source‐to‐drain (S/D) and gate‐dielectric (G/D) tunneling is essential to ensure optimal performance and reliability. In this study, numerical simulations of UTB‐SOI FETs are conducted to reveal their effects. First, for S/D tunneling, only a p‐channel FET (PFET) is considered critical, and larger tunneling mass eases this problem. Second, for G/D tunneling, an n‐channel FET (NFET) is considered critical. Therefore, the oxide‐wall UTB‐SOI design is considered for the NFET, enabling a large and small ratios for NFET and PFET. Conversely, the conventional trenched UTB‐SOI is considered suitable for PFET. Moreover, the findings demonstrate that adopting hafnium oxide (HfO) as the oxide material renders good FET characteristics. The optimized FET designs can facilitate the minimum gate length to be 1 nm or shorter, especially for NFETs.

Interfacial Electronic Charge Trapping and Photonic Carrier Excitation Coupling in Solution-Processed Zinc-Tin Oxide Thin-Film Transistors Applied for Logic Gate Design and Quantized Neural Network.

Components needed in Artificial Intelligence with a higher information capacity are critically needed and have garnered significant attention at the forefront of information technology. This study utilizes solution-processed zinc-tin oxide (ZTO) thin-film phototransistors and modulates the values of VG, which allows for the regulation of electron trapping/detrapping at the ZTO/SiO2 interface. By coupling the excited photonic carrier and electronic trapping, logic gates such as "AND," "OR," "NAND," and "NOR" can be achieved. With the exponential growth in data generation, efficient processing and storage solutions are imperative. However, extensive data transfer between computing units and storage limits the level of artificial neural networks (ANNs). Consequently, quantized neural networks (QNNs) have gained interest for their reduced computational resource requirements and lower consumption. In this context, we introduce an optimized ternary logic circuit based on ZTO devices. By utilizing optical modulation to adjust the turn-on voltage of the single device, we demonstrate the achievement of ternary current states, thereby providing three distinct discrete states. This configuration can be extended to QNN computing, demonstrating multilevel quantized current values for in-memory computation. We achieved a handwriting digit recognition rate of 91.6%, thereby demonstrating reliable QNN hardware performance. This robust QNN performance indicates that the metal oxide phototransistor shows significant potential for future ternary computing systems.

Novel Design of EXOR Gate and its Application for Circuits using QCA Nanotechnology

Novel Design of EXOR Gate and its Application for Circuits using QCA Nanotechnology

Reconfigurable van der Waals Junction Field Effect Transistor with Anchored Threshold and Enhanced Subthreshold Swing for Complementary Logic.

The emergence of reconfigurable field effect transistors has introduced a more efficient method for realizing reconfigurable circuits, significantly lowering hardware overhead and enhancing versatility. However, these devices often suffer from asymmetric transfer curves, impacting logic gate performance and reliability. This work investigates the use of the van der Waals junction field effect transistor (JFET) for reconfigurable circuit applications. We present a reconfigurable JFET realized through WSe2/MoS2 van der Waals integrated heterojunctions with an optimized polarity gate design that effectively addresses the issues of unmatched threshold voltages between n- and p- FETs while also anchoring threshold voltages and reducing subthreshold swing. A complementary reconfigurable JFET inverter with the proposed gate design was demonstrated, showcasing excellent switching characteristics, symmetric transfer characteristics, and reduced power consumption, achieving a noise margin of 96.3% and a high gain of 153.82. The study further demonstrates the construction of reconfigurable NOR/NAND and XOR/XNOR logic gates with symmetric profiles and sharp switching, underscoring the versatility and effectiveness of the proposed approach. These findings highlight the potential of WSe2/MoS2 JFETs in advancing low-power, high-performance, reconfigurable electronic circuits within the CMOS framework.

Analysis of trapping effects on DC and RF performance in double Π-gate Al0.3Ga0.7N/GaN MOSHEMTs

Abstract This study investigates trap analysis of the DC and RF performance of Al0.3Ga0.7N/GaN Metal-Oxide-Semiconductor high electron mobility transistor (MOSHEMT) with double π-gate technology. The motivation behind double π-gate technology is to evenly distribute the peak electric field and reduce hot electron generation. This gate design helps to lower hot-electron generation across various operating conditions while maintaining device performance, particularly in the lower millimeter-wave frequency range. High dielectric constant HfO2 is used as gate oxide, which helps to lower the gate leakage current. Near the conduction band (CB), the electron quasi-fermi level of 30 meV is achieved. The practical application of HfO2 in AlGaN/GaN HEMTs is limited by its high oxygen permeability, brittleness, and reactivity with moisture and CO2, which can cause mechanical stress and form hafnium carbonate, adversely affecting device performance. Future designs of the double-π gate structure could enhance electrostatic control, reduce short-channel effects, and improve high-frequency performance by scaling down gate dimensions and using high-k or novel dielectric materials. Additionally, optimization for mm-wave and THz applications would help to maintain electron mobility and minimize parasitic capacitance and resistance.

Low-Power Design of Fully Digital BPSK Modulator and Demodulator Utilizing Nanoscale FinFET for Smart Implants

This study aims to create a high-speed, low-power data transmission solution for implantable medical devices based on cutting-edge FinFET technology. The work examines the application of Binary Phase Shift Keying (BPSK) modulation through a transmission gate design, which provides an optimal blend of low resistance, high-speed performance, and minimal power consumption. Additionally, the work includes the design of a sine-to-square wave converter and a modulating signal generator. FinFET is employed owing to its high switching speed, low power consumption, low leakage current, and excellent tolerance of short channel effects. The design exhibits a steady electric field at the source end, a high electrostatic potential, and an improved ON current at low work function values using Sentaurus TCAD simulations of a 20nm FinFET, allowing high-speed data modulation in smart implants. A nonoverlapping phase generator, a low-power, current-starved gated ring oscillator, a frequency divider utilizing a True Single Phase Clock D-Flip-flop, and an XOR gate serving as a pulse counter are all featured in the design of the BPSK demodulator. This work is significant for its ability to drastically reduce power consumption to 1.75μW while retaining high data transmission speeds, making it perfect for next-generation implantable medical devices. With a 0.9 V power supply, this FinFET-based BPSK modulator and demodulator achieve a far lower power consumption than conventional CMOS-based designs, which increases device longevity and efficiency in settings with limited resources.

Simulation and Experimental Study on Enhancing Dimensional Accuracy of Polycarbonate Light Guides.

This research investigates the adaptation of conventional injection-molding techniques for producing thick-walled polycarbonate optical components, specifically targeting their application in automotive light guides. With the automotive industry's growing demand for reliable yet cost-efficient optical products, the study examines how traditional injection-molding processes can be refined to enhance dimensional accuracy and reduce defects. Simulations and experimental trials were conducted to evaluate the impact of critical process parameters, such as melt temperature, mold temperature, injection pressure, and gate design, on the overall quality of the final components. The results show that by carefully optimizing these parameters, it is possible to significantly reduce common defects like warpage, surface imperfections, and dimensional instability. This research highlights the potential of existing molding techniques to meet high industry standards while maintaining cost-effectiveness, offering valuable guidance for manufacturers aiming to produce high-quality optical components for demanding applications like automotive lighting.

Design and optimisation of automated hydraulic gate control systems for flood control

The study was conducted to analyse the design and optimisation of automated hydraulic gate control systems for effective flood control. It used data analysis from water level sensors, modelling of hydraulic systems, and control algorithms to automate the monitoring of hydraulic locks. As a result of the study, key aspects that confirm the importance of automation of hydraulic gate control for effective flood control were identified. It was established that the introduction of radiofrequency and ultrasonic sensors for water level monitoring provided a high level of data accuracy, which allowed responding in a timely manner to rising water levels. Adaptive control algorithms allowed optimising the operation of gates in dynamic conditions, considering changes in hydrodynamic characteristics. In addition, analysis of gate stability showed that the use of modern materials, such as high-strength steels and composites, substantially increased their durability and corrosion resistance. This was an important factor in ensuring the reliable operation of structures in extreme conditions. The examined models of the dynamic behaviour of gates identified critical zones that are subject to special attention during design since they can be destroyed under the influence of hydrodynamic forces. Overall, the results of the study highlighted the importance of integrating modern technologies into the design of hydraulic systems to improve their functionality and reliability in flood-risk situations. The influence of vibrations and resonant phenomena on the gate structures was analysed, which allowed identifying possible risks for their stability in flood conditions. As a result, recommendations for gate design included structural improvements that help reduce dynamic loads and improve their ability to withstand extreme hydrodynamic conditions

Peran Gerbang dan Tembok Penyengker Rumah Vernakular Bali dalam Pengendalian Kebisingan Ruang Luar

<p><em>Apart from functioning as a barrier to houses and other properties, gates can also function as a noise barrier. The gates in Balinese vernacular houses have various typologies and are equipped with locking walls which can act as a noise barrier against sounds coming from the street into the house. This research is a case study research, using a field survey method. The type of gate studied is the cangkem frog type which has a free yard and is located on the collector road. Data was obtained through direct observation and measurement using a sound level meter to determine the results of field measurements. This research shows that choosing the design and location of gates and tension walls as well as adding gates can reduce traffic noise by 5 to 13 dB.</em></p>

Implementation of EXOR and Subsequent Modular Circuits for Application at Nanoscale Level

Evolving as an outperforming nanotechnology, quantum-dot cellular automata (QCA) is being efficiently used for the design and development of digital modules. This paper presents a novel design for an ultra-efficient exclusive-OR (EXOR) gate in QCA nanotechnology using the cell translation technique. The analysis for fault tolerance and power dissipation of the proposed design is also assessed. To establish the effectiveness of the proposed design, an extensive comparison with the existing designs is provided. As a test bench implementation, the proposed EXOR gate is available as a module for the development of a parity checker, a full subtractor, and a 4-input binary to gray (B2G) code converter in QCA. The cell count for the proposed design of the EXOR gate, full subtractor, parity checker, and 4-input B2G converter is 8, 35, 24, and 24, and the total area (µm2) is 0.0039, 0.0259, 0.01749, and 0.0129, respectively. The proposed EXOR gate design outclasses the hitherto prevailing designs both in terms of the operational parameters and the dissipation of energy. The design simulations have been performed in QCA Designer 2.0.3, and the energy dissipation analysis has been executed in QCA Designer-E and QCAPro.

Reducing the effect of noise on quantum gate design by linear filtering

Reducing the effect of noise on quantum gate design by linear filtering

Eye-tracking investigation of emotional feedback to southern Hebei courtyard gates

ABSTRACT The attention of residents has always been drawn to the courtyard gates of rural residential buildings, this is the basis for evaluating the first impression of the countryside by first-time visitors. Using eye-tracking technology, this study measures the pupil diameter, fixation duration, and fixation point of subjects as objective physiological data, Then combined with the results of the subjective satisfaction questionnaire for a comprehensive analysis. The findings showed that, When the subjects evaluated their satisfaction with the courtyard gates, the proportion and color of the modeling elements led to the subjects’ emotional changes, and the subjects focused mainly on the central axis and the connection of various structures with raised areas. In order to elicit positive emotions in the subjects, village gate designs should therefore adhere to the standard specification’s requirements as well as the following: the width of the gate should be 0.8 times the height, the height should be 5 times the width of the gateposts, and the color should match the material’s color. To meet the emotional needs of the visitors, the final design strategy of the proportion and color of rural courtyard gates in southern Hebei Province is proposed.

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.