Design Space Exploration Research Articles

Design Space Exploration of Clustered Sparsely Connected MPSoC Platforms.

Heterogeneous multiprocessor platforms are the foundation of systems that require high computational power combined with low energy consumption, like the IoT and mobile robotics. In this paper, we present five new algorithms for the design space exploration of platforms with elements grouped in clusters with very few connections in between, while these platforms have favorable electric properties and lower production costs, the limited interconnectivity and inability of heterogeneous platform elements to execute all types of tasks, significantly decrease the chance of finding a feasible mapping of application to the platform. We base the new algorithms on the Non-dominated Sorting Genetic Algorithm II (NSGA-II) meta-heuristic and the previously published SDSE mapping algorithm designed for fully interconnected multiprocessor platforms. With the aim to improve the chance of finding feasible solutions for sparsely connected platforms, we have modified the parts of the search process concerning the penalization of infeasible solutions, chromosome decoding, and mapping strategy. Due to the lack of adequate existing benchmarks, we propose our own synthetic benchmark with multiple application and platform models, which we believe can be easily extended and reused by other researchers for further studying this type of platform. The experiments show that four proposed algorithms can find feasible solutions in 100% of test cases for platforms with dedicated clusters. In the case of tile-like platforms, the same four algorithms show an average success rate of 60%, with one algorithm going up to 84%.

Architectural and Technological Improvements to Integrated Bioprocess Models towards Real-Time Applications.

Integrated or holistic process models may serve as the engine of a digital asset in a multistep-process digital twin. Concatenated individual-unit operation models are effective at propagating errors over an entire process, but are nonetheless limited in certain aspects of recent applications that prevent their deployment as a plausible digital asset, particularly regarding bioprocess development requirements. Sequential critical quality attribute tests along the process chain that form output–input (i.e., pool-to-load) relationships, are impacted by nonaligned design spaces at different scales and by simulation distribution challenges. Limited development experiments also inhibit the exploration of the overall design space, particularly regarding the propagation of extreme noncontrolled parameter values. In this contribution, bioprocess requirements are used as the framework to improve integrated process models by introducing a simplified data model for multiunit operation processes, increasing statistical robustness, adding a new simulation flow for scale-dependent variables, and describing a novel algorithm for extrapolation in a data-driven environment. Lastly, architectural and procedural requirements for a deployed digital twin are described, and a real-time workflow is proposed, thus providing a final framework for a digital asset in bioprocessing along the full product life cycle.

0D Physics-Based Modeling of High Energy Lithium Metal Batteries with Pulsing Requirements

Lithium metal batteries are promising candidates for high energy storage solutions. To further increase capacity, electrolyte components can have a secondary function of storing charge through electrochemical reactions. This work focuses on modeling high-energy lithium metal anode and metal oxide cathode material and potentially other materials with additional capacity from electrolyte components. Physics-based modeling can be utilized to explore design space and predict battery performance under various conditions. This work utilizes a zero-dimensional model with thermodynamics, kinetics, transport, and morphology changes of the solution and solid-phase species. The effect of the additional electrolyte components on the transport, capacity, and voltage behavior will be explored. Pulse power will also be discussed, and this talk may include comparisons to experimental data.

Model-driven design space exploration for multi-robot systems in simulation

Multi-robot systems are increasingly deployed to provide services and accomplish missions whose complexity or cost is too high for a single robot to achieve on its own. Although multi-robot systems offer increased reliability via redundancy and enable the execution of more challenging missions, engineering these systems is very complex. This complexity affects not only the architecture modelling of the robotic team but also the modelling and analysis of the collaborative intelligence enabling the team to complete its mission. Existing approaches for the development of multi-robot applications do not provide a systematic mechanism for capturing these aspects and assessing the robustness of multi-robot systems. We address this gap by introducing ATLAS, a novel model-driven approach supporting the systematic design space exploration and robustness analysis of multi-robot systems in simulation. The ATLAS domain-specific language enables modelling the architecture of the robotic team and its mission and facilitates the specification of the team’s intelligence. We evaluate ATLAS and demonstrate its effectiveness in three simulated case studies: a healthcare Turtlebot-based mission and two unmanned underwater vehicle missions developed using the Gazebo/ROS and MOOS-IvP robotic platforms, respectively.

Design Space Exploration of Antenna Impedance and On-Chip Rectifier for Microwave Wireless Power Transfer

This paper discusses a design methodology to efficiently determine the best combination of rectenna (rectifier and antenna) to minimize the input power under a given output condition for microwave wireless power transfer (MWPT) without any other external components, such as a matching network, for cost reduction. A linearized equivalent circuit model is expanded upon to include the microstrip line connecting the antenna and rectifier. Based on the model, the design flow is presented that has mainly three steps: (1) Determination of the equivalent rectifier input impedance and the amplitude of input voltage by running SPICE simulation, (2) Drawing contour plots of input power by rectifier candidate on the antenna impedance plane by conducting model calculation and impedance loci of antenna candidates on the contour plots, and (3) Selecting the combination of antenna and rectifier which gives the minimum input power for all the combinations. To validate the equivalent circuit model and design flow, a single-diode (SD) rectifier and a voltage-doubler (VD) rectifier were fabricated in 65 nm CMOS. The input power to generate 100 μA at 1 Vdc was measured and compared. The model, SPICE and measurement are in good agreement with each other that VD has 30–50% lower input power than SD does. In addition, the sensitivity of the parasitic elements, such as the microstrip line and the bonding wires and pads on the input power, are investigated to explore the design space for rectenna.

Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations

Silicon photonic microring resonators (MRRs) offer many advantages (e.g., compactness) and are often considered as the fundamental building block in optical interconnects and emerging photonic nanoprocessors and accelerators. Such devices are, however, sensitive to inevitable fabrication-process variations (FPVs) stemming from optical lithography imperfections. Consequently, silicon photonic integrated circuits (PICs) integrating MRRs often suffer from high power overhead required to compensate for the impact of FPVs on MRRs and, hence, realizing a reliable operation. On the other hand, the design space of MRRs is complex, including several correlated design parameters, thereby further exacerbating the design optimization of MRRs under FPVs. In this article, we present, for the first time, a comprehensive design-space exploration in passive and active MRRs under FPVs. In addition, we present design optimization in MRRs under FPVs while considering different performance metrics, such as tolerance to FPVs, quality factor, and 3-dB bandwidth in MRRs. Simulation and fabrication results obtained by measuring multiple fabricated MRRs designed using our design-space exploration demonstrate a significant 70% improvement on average in the MRRs’ tolerance to different FPVs. Furthermore, we apply the proposed design optimization to a case study of a wavelength-selective MRR-based demultiplexer, where we show considerable channel-spacing accuracy within 0.5 nm even when the MRRs are placed 500 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> apart on a chip. Such improvements indicate the efficiency of the proposed design-space exploration and optimization to enable power-efficient and variation-resilient PICs and optical interconnects integrating MRRs.

On the combination of dynamic substructuring and surrogate modeling for the design and study of complex systems

For decades, dynamic substructuring approaches have been successfully utilized for the modeling and simulation of complex systems. More recently, surrogate modeling methods have emerged as a way to reduce the computational cost of simulating for design. This talk will introduce a paradigm in which these two techniques may be combined for the design and study of complex systems. For illustration, a simple example is put forward in which a mass-spring system is broken into subsystems and parameterized. The open-source Python package SMT (Surrogate Modeling Toolbox) developed and maintained by Bouhel et al. is used to construct surrogate models for each subsystem in which the component parameters are taken as inputs and the frequency response functions (FRFs) of the interface degrees of freedom are output. These FRFs are then used to construct the response of the fully coupled system by utilizing a dual Frequency Based Substructuring technique. In many real-world applications, this manner of calculating the effect of varying design parameters on the system response is likely more practical and computationally feasible than the alternative of directly simulating the coupled system response for many parameter sets and training a surrogate model from that output for further design space exploration and optimization. [Work supported by the Office of Naval Research]

Design space exploration and decision‐making for a segmented ultralight morphing 50‐MW wind turbine

AbstractWind turbine design encompasses many different aspects including aerodynamic, structural, electrical, and control system design. To achieve optimal plant performance, a system design approach is utilized in which the performance of the whole wind turbine is evaluated and quantified during operational scenarios with subsystem interactions. In this paper, the design for a Segmented Ultralight Morphing Rotor (SUMR) 50‐MW wind turbine is presented utilizing levelized cost of energy (LCOE) for design choices, with additional quantification of simulated performance shortcomings at the 50‐MW scale. The multi‐disciplinary design process results in a final ultra‐scale turbine configuration that outperforms other existing offshore wind farms regarding the LCOE.

Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis

In this paper, we present a machine learning based High-Level Synthesis (HLS) design space explorer (DSE) that significantly reduces the exploration runtime while leading to very accurate results. In order to do so, we leverage the power of low level virtual machine (LLVM) to generate the features used in the machine learning (ML) model. The proposed design space explorer uses a modified version of simulated annealing (SA) algorithm, where initially the search space is sampled to generate the predictive model. In this work we used gradient boost regression algorithm as our preferred ML model and achieve comparable results as a full DSE that performs logic synthesis for each newly generated design.

An OpenCL-Based FPGA Accelerator for Faster R-CNN

In recent years, convolutional neural network (CNN)-based object detection algorithms have made breakthroughs, and much of the research corresponds to hardware accelerator designs. Although many previous works have proposed efficient FPGA designs for one-stage detectors such as Yolo, there are still few accelerator designs for faster regions with CNN features (Faster R-CNN) algorithms. Moreover, CNN’s inherently high computational complexity and high memory complexity bring challenges to the design of efficient accelerators. This paper proposes a software-hardware co-design scheme based on OpenCL to implement a Faster R-CNN object detection algorithm on FPGA. First, we design an efficient, deep pipelined FPGA hardware accelerator that can implement Faster R-CNN algorithms for different backbone networks. Then, an optimized hardware-aware software algorithm was proposed, including fixed-point quantization, layer fusion, and a multi-batch Regions of interest (RoIs) detector. Finally, we present an end-to-end design space exploration scheme to comprehensively evaluate the performance and resource utilization of the proposed accelerator. Experimental results show that the proposed design achieves a peak throughput of 846.9 GOP/s at the working frequency of 172 MHz. Compared with the state-of-the-art Faster R-CNN accelerator and the one-stage YOLO accelerator, our method achieves and inference throughput improvements, respectively.

E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning

Recently, Reinforcement Learning (RL) has shown great performance in solving sequential decision-making and control in dynamic environment problems. Despite its achievements, deploying Deep Neural Network (DNN)-based RL is expensive in terms of time and power due to the large number of episodes required to train agents with high dimensional image representations. Additionally, at the interference the large energy footprint of deep neural networks can be a major drawback. Embedded edge devices as the main platform for deploying RL applications are intrinsically resource-constrained and deploying deep neural network-based RL on them is a challenging task. As a result, reducing the number of actions taken by the RL agent to learn desired policy, along with the energy-efficient deployment of RL, is crucial. In this article, we propose Energy Efficient Hierarchical Reinforcement Learning (E2HRL), which is a scalable hardware architecture for RL applications. E2HRL utilizes a cross-layer design methodology for achieving better energy efficiency, smaller model size, higher accuracy, and system integration at the software and hardware layers. Our proposed model for RL agent is designed based on the learning hierarchical policies, which makes the network architecture more efficient for implementation on mobile devices. We evaluated our model in three different RL environments with different level of complexity. Simulation results with our analysis illustrate that hierarchical policy learning with several levels of control improves RL agents training efficiency and the agent learns the desired policy faster compared to a non-hierarchical model. This improvement is specifically more observable as the environment or the task becomes more complex with multiple objective subgoals. We tested our model with different hyperparameters to achieve the maximum reward by the RL agent while minimizing the model size, parameters, and required number of operations. E2HRL model enables efficient deployment of RL agent on resource-constraint-embedded devices with the proposed custom hardware architecture that is scalable and fully parameterized with respect to the number of input channels, filter size, and depth. The number of processing engines (PE) in the proposed hardware can vary between 1 to 8, which provides the flexibility of tradeoff of different factors such as latency, throughput, power, and energy efficiency. By performing a systematic hardware parameter analysis and design space exploration, we implemented the most energy-efficient hardware architectures of E2HRL on Xilinx Artix-7 FPGA and NVIDIA Jetson TX2. Comparing the implementation results shows Jetson TX2 boards achieve 0.1 ∼ 1.3 GOP/S/W energy efficiency while Artix-7 FPGA achieves 1.1 ∼ 11.4 GOP/S/W, which denotes 8.8× ∼ 11× better energy efficiency of E2HRL when model is implemented on FPGA. Additionally, compared to similar works our design shows better performance and energy efficiency.

A multi-fidelity active learning method for global design optimization problems with noisy evaluations

A multi-fidelity (MF) active learning method is presented for design optimization problems characterized by noisy evaluations of the performance metrics. Namely, a generalized MF surrogate model is used for design-space exploration, exploiting an arbitrary number of hierarchical fidelity levels, i.e., performance evaluations coming from different models, solvers, or discretizations, characterized by different accuracy. The method is intended to accurately predict the design performance while reducing the computational effort required by simulation-driven design (SDD) to achieve the global optimum. The overall MF prediction is evaluated as a low-fidelity trained surrogate corrected with the surrogates of the errors between consecutive fidelity levels. Surrogates are based on stochastic radial basis functions (SRBF) with least squares regression and in-the-loop optimization of hyperparameters to deal with noisy training data. The method adaptively queries new training data, selecting both the design points and the required fidelity level via an active learning approach. This is based on the lower confidence bounding method, which combines the performance prediction and the associated uncertainty to select the most promising design regions. The fidelity levels are selected considering the benefit-cost ratio associated with their use in the training. The method’s performance is assessed and discussed using four analytical tests and three SDD problems based on computational fluid dynamics simulations, namely the shape optimization of a NACA hydrofoil, the DTMB 5415 destroyer, and a roll-on/roll-off passenger ferry. Fidelity levels are provided by both adaptive grid refinement and multi-grid resolution approaches. Under the assumption of a limited budget for function evaluations, the proposed MF method shows better performance in comparison with the model trained by high-fidelity evaluations only.

Model driven design for integrated twin screw granulator and fluid bed dryer via flowsheet modelling

This paper presents a flowsheet modelling of an integrated twin screw granulation (TSG) and fluid bed dryer (FBD) process using a Model Driven Design (MDD) approach. The MDD approach is featured by appropriate process models and efficient model calibration workflow to ensure the product quality. The design space exploration is driven by the physics of the process instead of extensive experimental trials. By means of MDD, the mechanistic-based process kernels are first defined for the TSG and FBD processes. With the awareness of the underlying physics, the complementary experiments are carried out with relevance to the kinetic parameters in the defined models. As a result, the experiments are specifically purposeful for model calibration and validation. The L/S ratio (liquid to solid ratio) and inlet air temperature are selected as the Critical Process Parameters (CPPs) in TSG and FBD for model validation, respectively. Global System Analysis (GSA) is further performed to assess the uncertainty of CPPs imposed on the Critical Quality Attributes (CQAs), which provides significant insights to the exploration of the design space considering both TSG and FBD process parameters.

Flare-fork collaborative strategy: expanding design space via opportunistic ideation in engineering product design

&#x0D; &#x0D; &#x0D; Restricted exploration of design space is a problem that novice designers face when solving engineering product design problems. Consequences of limited exploration can be the generation of sub-optimal solutions and fixation towards the first solution idea or known solution space. Expert designers sift through their vast repertoire of solution alternatives and choose the appropriate solution for the given design problem. Novices, however, lack this vast repository of alternative solution approaches. Therefore, it is good practice for novices to expand the problem and solution space and explore different aspects of the product design problem before identifying solutions appropriate for the design problem.&#x0D; Flare-fork collaborative strategy is a design exploration strategy that enables designers to generate opportunistic ideas related to the design problem and integrate them during the design process thereby expanding problem and solution space. The flare-fork collaborative strategy leverages rapid ideation, and semantic analogy thought transformation strategy to generate new ideas, interlinking ideas in design space map (DSM) for the elaboration of ideas, and thought transformer strategy to manipulate ideas for expanding problem and solution space. This paper describes a study to examine how the operationalization of the flare aspect of flare-fork collaborative strategy as an intervention supports the design process of three teams of students. We found that students frequently traverse between problem and solution space via an intermediate bridge space. Also, regardless of where the students begin, they do a comprehensive exploration of problem and solution space while using flare-fork collaborative strategy. Students’ perception of using flare-fork collaborative strategy to explore engineering product design is predominantly positive, with students identifying several ways in which flare aspect of flare-fork collaborative strategy aided them in their expansion of problem and solution space.&#x0D; &#x0D; &#x0D;

Optimisation-driven design to explore and exploit the process–structure–property–performance linkages in digital manufacturing

An intelligent manufacturing paradigm requires material systems, manufacturing systems, and design engineering to be better connected. Surrogate models are used to couple product-design choices with manufacturing process variables and material systems, hence, to connect and capture knowledge and embed intelligence in the system. Later, optimisation-driven design provides the ability to enhance the human cognitive abilities in decision-making in complex systems. This research proposes a multidisciplinary design optimisation problem to explore and exploit the interactions between different engineering disciplines using a socket prosthetic device as a case study. The originality of this research is in the conceptualisation of a computer-aided expert system capable of exploring process–structure–property–performance linkages in digital manufacturing. Thus, trade-off exploration and optimisation are enabled of competing objectives, including prosthetic socket mass, manufacturing time, and performance-tailored socket stiffness for patient comfort. The material system is modelled by experimental characterisation—the manufacturing time by computer simulations, and the product-design subsystem is simulated using a finite element analysis (FEA) surrogate model. We used polynomial surface response-based surrogate models and a Bayesian Network for design space exploration at the embodiment design stage. Next, at detail design, a gradient descent algorithm-based optimisation exploits the results using desirability functions to isolate Pareto non-dominated solutions. This work demonstrates how advanced engineering design synthesis methods can enhance designers’ cognitive ability to explore and exploit multiple disciplines concurrently and improve overall system performance, thus paving the way for the next generation of computer systems with highly intertwined material, digital design and manufacturing workflows.Graphical abstract

Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking.

A design space exploration of the countermeasures for hardware masking is proposed in this paper. The assumption of independence among shares used in hardware masking can be violated in practical designs. Recently, the security impact of noise coupling among multiple masking shares has been demonstrated both in practical FPGA implementations and with extensive transistor level simulations. Due to the highly sophisticated interactions in modern VLSI circuits, the interactions among multiple masking shares are quite challenging to model and thus information leakage from one share to another through noise coupling is difficult to mitigate. In this paper, the implications of utilizing on-chip voltage regulators to minimize the coupling among multiple masking shares through a shared power delivery network (PDN) are investigated. Specifically, different voltage regulator configurations where the power is delivered to different shares through various configurations are investigated. The placement of a voltage regulator relative to the masking shares is demonstrated to a have a significant impact on the coupling between masking shares. A PDN consisting of two shares is simulated with an ideal voltage regulator, strong DLDO, normal DLDO, weak DLDO, two DLDOs, and two DLDOs with 180 phase shift. An 18 × 18 grid PDN with a normal DLDO is simulated to demonstrate the effect of PDN impedance on security. The security analysis is performed using correlation and t-test analyses where a low correlation between shares can be inferred as security improvement and a t-test value below 4.5 means that the shares have negligible coupling, and thus the proposed method is secure. In certain cases, the proposed techniques achieve up to an 80% reduction in the correlation between masking shares. The PDN with two DLDOs and two-phase DLDO with 180 phase shift achieve satisfactory security levels since t-test values remain under 4.5 with 100,000 traces of simulations. The security of the PDN improves if DLDO is placed closer to any one of the masking shares.

Battery Selection and Optimal Energy Management for a Range-Extended Electric Delivery Truck

&lt;div class="section abstract"&gt;&lt;div class="htmlview paragraph"&gt;Delivery trucks and vans represent a growing transportation segment which reflects the shift of consumers towards on-line shopping and on-demand delivery. Therefore, electrification of this class of vehicles is going to play a major role in the decarbonization of the transportation sector and in the transition to a sustainable mobility system. Hybrid electric vehicles can represent a medium-term solution and have gained an increasing share of the market in recent years. These vehicles include two power sources, typically an internal combustion engine and a battery, which gives more degrees of freedom when controlling the powertrain to satisfy the power request at the wheels. Components sizing and powertrain energy management are strongly coupled and can make a substantial impact on the final energy consumption of a hybrid vehicle. An optimal control problem can be formulated and solved off-line, to evaluate the most energy efficient utilization of fuel and battery energy for the specific vehicle design. These off-line solutions can be used as benchmarks to compare different architectures and design options, and rules can be derived from them to design on-line implementable heuristic control strategies. In this work a plug-in series architecture with a range-extender engine is considered for a Class 6 beverage delivery truck and the optimal control problem is solved using dynamic programming. To study the strong coupling that exists between components sizing and energy management a simulation design space exploration is performed with four different cell chemistries and three different battery pack sizes. A drive cycle with variable payload, which is representative of delivery operations, is developed and used as a test case. The results show how the selection of the cell chemistry and the constraints on the battery weight can affect the battery performance and the impact on the optimal energy management strategy.&lt;/div&gt;&lt;/div&gt;

The role of latent representations for design space exploration of floorplans

Floorplans often require considering numerous factors, from the layout size to cost, numeric attributes such as room sizes, and other intrinsic properties such as connectivity between visible regions. Representing these complex factors is challenging, but doing so in a representative and efficient way can enable new modes of design exploration. Existing image and graph-based approaches of floorplans’ representation often failed to consider low-level space semantics, structural features, and space utilization with respect to its future inhabitants, which are all the critical elements to analyze design layouts. We present a latent-space representation of floorplans using gated recurrent unit variational autoencoder (GRU-VAE), where floorplans are represented as attributed graphs (encoded with the abovementioned features). Two local search approaches are presented to efficiently explore the latent space for optimizing and generating new floorplans for the given environment. Semantic, structural, and visibility metrics are evaluated individually and as a combined objective for optimizations.

Fast Design Space Exploration of Nonlinear Systems: Part II

Nonlinear system design is often a multiobjective optimization problem involving the search for a design that satisfies a number of predefined constraints. The design space is typically very large since it includes all possible system architectures with different combinations of components composing each architecture. In this article, we address nonlinear system design space exploration through a two-step approach encapsulated in a framework called fast design space exploration of nonlinear systems (ASSENT). In the first step, we use a genetic algorithm to search for system architectures that allow discrete choices for component values or else only component values for a fixed architecture. This step yields a coarse design since the system may or may not meet the target specifications. In contrast to prior works on design space exploration that rely on forward design, we use an inverse design in step 2 to search over a continuous space and fine-tune the component values with the goal of improving the value of the objective function. We use a neural network (NN) to model the system response. The NN is converted into a mixed-integer linear program for active learning to sample component values efficiently. We illustrate the efficacy of ASSENT on problems ranging from nonlinear system design to the design of electrical circuits. Experimental results show that ASSENT achieves the same or better value of the objective function compared to various other optimization techniques for nonlinear system design by up to 53%. We improve sample efficiency by 6– <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12\times $ </tex-math></inline-formula> compared to reinforcement learning-based synthesis of electrical circuits.

Characterizing and Optimizing EDA Flows for the Cloud

Design space exploration in logic synthesis and parameter tuning in physical design require a massive amount of compute resources in order to meet tapeout schedules. To address this need, cloud computing provides semiconductor and electronics companies with instant access to scalable compute resources. However, deploying electronic design automation (EDA) jobs on the cloud requires EDA teams to deeply understand the characteristics of their jobs in cloud environments. Unfortunately, there has been little to no public information on these characteristics. Thus, in this article, we first formulate the problem of moving EDA jobs to the cloud. To address the problem, we characterize the performance of four EDA main applications, namely: 1) synthesis; 2) placement; 3) routing; and 4) static timing analysis. We show that different EDA jobs require different compute configurations in order to achieve the best performance. Using observations from our characterization, we propose a novel model based on graph convolutional networks to predict the total runtime of a given stage on different configurations. Our model achieves a prediction accuracy of 87%. Furthermore, we present a new formulation for optimizing cloud deployments in order to reduce costs while meeting deadline constraints. We present a pseudopolynomial optimal solution using a multichoice knapsack mapping that reduces deployment costs by 35.29%, with minimal overhead to the total runtime. In addition, we describe a cloud-ready solution, called EDA analytics central, for the continuous optimization of a design across an EDA flow. We used this system in building our runtime prediction model.