Design Space Exploration Of Architectures Research Articles

Architectural design space exploration of complex engineered systems with management constraints and preferences

During the architectural design phase, the decisions made have a crucial impact on developing complex systems. These decisions often limit the performance bounds and steer subsequent research directions. However, the multitude of architectural components and intricate interrelationships cause component combination explosion. Additionally, the diverse requirements of different stakeholders add complexity to determining the weight of indicators, posing challenges to complex system architecture generation and trade-off. This paper proposes a method for exploring the architectural design space in complex systems realisation, which aims to resolve issues related to the formal representation of architectures, selection within the architectural design space, and trade-offs. Firstly, the architectural design space is represented by formulating and mathematically describing a morphological matrix. Then, the construction of the Constraint Satisfaction Problem model aims to achieve a reduction in the scale of the design space. Moreover, through the evolutionary algorithm, the Pareto front is identified. Weight sensitivity analysis and the improved Technique for Order Preference by Similarity to the Ideal Solution method are combined to assist designers in finding a satisfactory architecture from the design space with many combinations. Finally, the proposed method is verified by the design of the launch vehicle’s primary and secondary separation system.

Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis

This effort develops the first rich suite of analog and mixed-signal benchmark of various sizes and domains, intended for use with contemporary analog and mixed-signal designs and synthesis tools. Benchmarking enables analog-digital co-design exploration as well as extensive evaluation of analog synthesis tools and the generated analog/mixed-signal circuit or device. The goals of this effort are defining analog computation system benchmarks, developing the required concepts for higher-level analog and mixed-signal tools to utilize these benchmarks, and enabling future automated architectural design space exploration (DSE) to determine the best configurable architecture (e.g., a new FPAA) for a certain family of applications. The benchmarks comprise multiple levels of an acoustic , a vision , a communications , and an analog filter system that must be simultaneously satisfied for a complete system.

ExDe: Design space exploration of scheduler architectures and mechanisms for serverless data-processing

Serverless computing is increasingly used for data-processing applications in both science and business domains. At the core of serverless data-processing systems is the scheduler, which ensures dynamic decisions about task and data placement. Due to the variety of user, cluster, and workload properties, the design space for high-performance and cost-effective scheduling architectures and mechanisms is vast. The large design space is difficult to explore and characterize. To help the system designer disentangle this complexity, we present ExDe, a framework to systematically explore the design space of scheduling architectures and mechanisms. The framework includes a conceptual model and a simulator to assist in design space exploration.We use the framework, and real-world workloads, to characterize the performance of three scheduling architectures and two mechanisms. Our framework is open-source software available on Zenodo.

Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays

The architecture of a coarse-grained reconfigurable array (CGRA) interconnect has a significant effect on not only the flexibility of the resulting accelerator, but also its power, performance, and area. Design decisions that have complex trade-offs need to be explored to maintain efficiency and performance across a variety of evolving applications. This paper presents Canal, a Python-embedded domain-specific language (eDSL) and compiler for specifying and generating reconfigurable interconnects for CGRAs. Canal uses a graph-based intermediate representation (IR) that allows for easy hardware generation and tight integration with place and route tools. We evaluate Canal by constructing both a fully static interconnect and a hybrid interconnect with ready-valid signaling, and by conducting design space exploration of the interconnect architecture by modifying the switch box topology, the number of routing tracks, and the interconnect tile connections. Through the use of a graph-based IR for CGRA interconnects, the eDSL, and the interconnect generation system, Canal enables fast design space exploration and creation of CGRA interconnects.

Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures

This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (AxM) combined with approximate adder (AxA) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of AxMs – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), leading one Bit-based Approximate (LoBA), and Truncated approach – jointly with the LOA, ETA-I, CopyA, CopyB, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> least-significant bits, respectively, for the AxM and AxA), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the LoBA multiplier with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> =8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality.

Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoC

Multi-core systems-on-chip are becoming state-of-the-art. Therefore, there is a need for a fast and energy-efficient interconnect to take full advantage of the computational capabilities. Integration of silicon photonics with a traditional electrical interconnect in a Network-on-Chip (NoC) proposes a promising solution for overcoming the scalability issues of electrical interconnect. In this article, we derive and evaluate prediction modeling techniques for the design space exploration (DSE) of application-specific communication architectures for an Optical Network-on-Chip (ONoC). Our proposed model accurately predicts network packet latency, contention delay, and the static and dynamic energy consumption of the network. This work specifically addresses the challenge of accurately estimating performance metrics of the entire design space without having to perform time-consuming and computationally intensive exhaustive simulations. The proposed technique, based on machine learning (ML), can build accurate prediction models using only 10% to 50% (best case and worst case) of the entire design space. The accuracy, expressed as R 2 (Coefficient of Determination) is 0.99901, 0.99967, 0.99996, and 0.99999 for network packet latency, contention delay, static energy consumption, and dynamic energy consumption, respectively, in six different benchmarks from the Splash-2 benchmark suite, chosen among 6 different machine learning prediction models.

LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures

Extensive large-scale data and applications have increasing requests for high-performance computations which is fulfilled by Chip Multiprocessors (CMP) and System-on-Chips (SoCs). Network-on-Chips (NoCs) emerged as the reliable on-chip communication framework for CMPs and SoCs. NoC architectures are evaluated based on design parameters such as latency, area, and power. Cycle-accurate simulators are used to perform the design space exploration of NoC architectures. Cycle-accurate simulators become slow for interactive usage as the NoC topology size increases. To overcome these limitations, we employ a Machine Learning (ML) approach to predict the NoC simulation results within a short span of time. LBF-NoC: Learning-based framework is proposed to predict performance, power and area for Direct and Indirect NoC architectures. This provides chip designers with an efficient way to analyze various NoC features. LBF-NoC is modeled using distinct ML regression algorithms to predict overall performance of NoCs considering different synthetic traffic patterns. The performance metrics of five different (Mesh, Torus, Cmesh, Fat-Tree and Flattened Butterfly) NoC architectures can be analyzed using the proposed LBF-NoC framework. BookSim simulator is employed to validate the results. Various architecture sizes from [Formula: see text] to [Formula: see text] are used in the experiments considering various virtual channels, traffic patterns, and injection rates. The prediction error of LBF-NoC is 6% to 8%, and the overall speedup is [Formula: see text] to [Formula: see text] with respect to BookSim simulator.

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation-hardened variants present superior resiliency when either local or global triple modular redundancy (TMR) schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes.

Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture

Deep neural networks (DNNs) have been shown to outperform conventional machine learning algorithms across a wide range of applications, e.g., image recognition, object detection, robotics, and natural language processing. However, the high computational complexity of DNNs often necessitates extremely fast and efficient hardware. The problem gets worse as the size of neural networks grows exponentially. As a result, customized hardware accelerators have been developed to accelerate DNN processing without sacrificing model accuracy. However, previous accelerator design studies have not fully considered the characteristics of the target applications, which may lead to sub-optimal architecture designs. On the other hand, new DNN models have been developed for better accuracy, but their compatibility with the underlying hardware accelerator is often overlooked. In this article, we propose an application-driven framework for architectural design space exploration of DNN accelerators. This framework is based on a hardware analytical model of individual DNN operations. It models the accelerator design task as a multi-dimensional optimization problem. We demonstrate that it can be efficaciously used in application-driven accelerator architecture design: we use the framework to optimize the accelerator configurations for eight representative DNNs and select the configuration with the highest geometric mean performance. The geometric mean performance improvement of the selected DNN configuration relative to the architectural configuration optimized only for each individual DNN ranges from 12.0 to 117.9 percent. Given a target DNN, the framework can generate efficient accelerator design solutions with optimized performance and area. Furthermore, we explore the opportunity to use the framework for accelerator configuration optimization under simultaneous diverse DNN applications. The framework is also capable of improving neural network models to best fit the underlying hardware resources. We demonstrate that it can be used to analyze the relationship between the operations of the target DNNs and the corresponding accelerator configurations, based on which the DNNs can be tuned for better processing efficiency on the given accelerator without sacrificing accuracy.

Design Space Exploration of High-Performance Parallel Architectures

High-performance single-threaded processors achieve their performance goal partly by relying, among other architectural techniques, on speculation and large on-chip caches. The hardware to support these techniques is usually a large portion of the overall processor real state area, and therefore it consumes a significant amount of power that sometimes is not optimally used toward doing useful work. In this work, we study the intuitive fact that architectures with hardware support for threads are more power efficient than a more traditional single-threaded superscalar architecture. Toward this goal, we have created a model of the power, performance and area of several parallel architectures. This model shows that a parallel architecture can be designed so that (a) it requires less area and power (to reach the same performance), or (b) it achieves better power efficiency and less area (for the same power budget), or (c) it has higher performance and better power efficiency (for the same area constraint), when compared to a single-threaded superscalar architecture.

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor

This paper proposes a high power-performance-area efficient background noise aware keyword-spotting (KWS) processor based on an optimized binarized weight network (BWN). To reduce the power consumption while maintaining the system recognition accuracy for different background noise, the KWS processor with a SNR prediction module can be adaptively configured to use dual computing modes (standard computing mode and approximate computing mode) for both high recognition accuracy under high background noise and ultra-low power consumption under low background noise. The mel-scale frequency cepstral coefficients (MFCC) module is optimized with approximate computing technologies, which can reduce the power consumption by up to $3.1\times $ and $5.7\times $ for high/low background noise, respectively. Based on the evaluation of the architecture design space exploration, an ultra-low power BWN accelerator with low voltage, area and leakage power and using precision self-adaptive approximate computing units was proposed. Evaluated under 22nm process technology, this work can support up to 10 keywords real time recognition with power consumption of $15.1~\mu \text{W}$ for high background noise and $10.8~\mu \text{W}$ for low background noise. Compared to the state-of-the-art KWS architectures, our work can achieve ultra-low power consumption (about $1.7\times $ reduced), while maintaining high system capability and adaptability.

Design Space Exploration of Stochastic Computing Architectures Implemented Using Integrated Optics

Approximate computing allows to trade-off design energy efficiency with computing accuracy. Stochastic computing is an approximate computing technique, where numbers are represented as bit streams corresponding to probabilities. The serial computation of the bit streams leads to reduced hardware complexity but involves high latency, which is the main limitation of the technique. Integrated optics technology relies on high propagation speed of signals, which has the potential to reduce the processing latency in stochastic computing. However, the design of stochastic computing architectures implemented using integrated optics involves the exploration of numerous parameters at system and technological levels. In this work, we propose a design space exploration framework that allows to optimize energy efficiency, computing accuracy, and latency of such architectures. The efficiency of the framework is evaluated using a Gamma correction image processing application. Results show that, for processing 160x160 pixels images, an acceptable ×4.5 increase in the errors leads to ×47 energy efficiency and ×16 processing speed. We also show that the same computing accuracy can be obtained for different energy efficiency and computing latency, thus, validating the ability of the framework to explore the design space.

Classification and Design Space Exploration of Low-Power Three-Stage Operational Transconductance Amplifier Architectures for Wide Load Ranges

Since operational transconductance amplifiers (OTAs) form the basic building blocks of many analog systems, the compensation of three-stage OTAs has attracted a lot of attention in the literature. Many different solutions to the stability problem of such OTAs have been proposed over the past 20 years, with each solution exhibiting different properties or targeting a different application. This work surveys a broad selection of previously reported architectures and proposes a novel classification scheme that exposes features common to seemingly different compensation architectures and serves as a guideline for which type of OTA is suitable for a given application. In addition, a novel figure of merit (FoM) is proposed to guide the designer in deciding which OTA architecture suits the tradeoffs specific to the application at hand. Theoretical discussions are further reinforced by transistor-level simulation results.

A framework to generate domain-specific manycore architectures from dataflow programs

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

An intelligent design method for actuation system architecture optimization for more electrical aircraft

The design of flight control actuation system is facing major challenge due to the development of more electrical aircraft. The task is to find the combinations of power sources, actuators and computers, which becomes more complex because of the new power sources and actuator types of more electrical aircraft. It is impossible to determine optimal architecture by traditional trial-and-error method within acceptable time. Therefore, the need for new methodology for actuation system architecture design emerges. This study proposes an intelligent design method which has steps of design space exploration of actuation system architectures by constraint satisfaction problem (CSP) method, safety assessment process to exclude unsafety solution, multi-objectives optimization to get Pareto optimal front and comprehensive decision for final architecture via analytic hierarchy process. And the design method is implemented in python and a software platform is developed. Furthermore, within the paper a case study for A350 flight control actuation system is presented to testify the application of this methodology. Compared to the traditional hydraulic architecture, the optimal architecture is more competitive in weight, power and cost. At the same time, the optimal architecture is found in less than 30 minutes among 1075 candidates, which greatly reduces the design cycle. This method deals with the problem in the design of flight control actuation system.

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies. NeuroSim provides flexible interface and a wide variety of design options at the circuit and device level. Therefore, NeuroSim can be used by neural networks (NNs) as a supporting tool to provide circuit-level performance evaluation. With NeuroSim, an integrated framework can be built with hierarchical organization from the device level (synaptic device properties) to the circuit level (array architectures) and then to the algorithm level (NN topology), enabling instruction-accurate evaluation on the learning accuracy as well as the circuit-level performance metrics at the run-time of online learning. Using multilayer perceptron as a case-study algorithm, we investigated the impact of the “analog” emerging nonvolatile memory (eNVM)’s “nonideal” device properties and benchmarked the tradeoffs between SRAM, digital, and analog eNVM-based architectures for online learning and offline classification.

Functional Model-Based Design Methodology for Automotive Cyber-Physical Systems

The high complexity of cross-domain engineering in combination with the pressure for system innovation, higher quality, time to market, and budget constraints makes it imperative for automotive companies to use integrated engineering methods and tools. Computer engineering tools are mainly focused on a particular domain, and therefore, it is difficult to integrate different tools for system-level analysis. In this paper, a novel multidisciplinary systems engineering methodology and associated design automation algorithms for the complex automotive cyber-physical systems are presented. Rather than starting from the domain-specific architecture/simulation models where most resources are spent, we preemptively target the early design stage at the functional level that determines 75% of an automobile's cost. In our methodology, the marriage of systems engineering principles with high-level synthesis techniques from design automation area results in a functional modeling compiler capable of generating high-fidelity simulation models for the design space exploration and validation of multiple cyber-physical automotive architectures. Using real-world automotive use cases, we demonstrate how functional models capturing integrated cyber-physical aspects are synthesized into high-fidelity multidomain simulation models.

Optimizing energy and throughput for MPSoCs: an integer particle swarm optimization approach

Most of recent research in multicore processor architectures has been shifted towards reconfigurable architectures due to increasing complexity of computing systems. These systems provide better application-specific energy and throughput balance with their reconfigurable behavior. They perform automatic run time resource allocation for an application as per its needs. But in terms of performance, current methodologies produce some unpredictable results because of the actual variety of the workloads. Therefore, we need optimization of the system resources usage by employing some optimization algorithms. Early research in the field of reconfigurable architecture using optimization algorithms has produced efficient results for energy consumption with the reconfiguration of cache sizes and associativity, number of cores and operating frequency. In this research, we propose particle swarm optimization (PSO) based algorithm, Integer PSO (IPSO) for design space exploration of reconfigurable computer architectures to have better energy and throughput balance. The results obtained by IPSO are evaluated by using various SPLASH-2 benchmark applications. Evaluation shows notable reduction in energy consumption without major effect on throughput. Simulation results also support the use of IPSO in design space exploration of multicore reconfigurable processor architectures.

Optimal Design Space Exploration of Multi-core Architecture for Real-time Lane Detection Algorithm

Optimal Design Space Exploration of Multi-core Architecture for Real-time Lane Detection Algorithm

Optimal Design Space Exploration of Multi-core Architecture for Real-time Lane Detection Algorithm

Optimal Design Space Exploration of Multi-core Architecture for Real-time Lane Detection Algorithm