Design Space Exploration Method Research Articles

Robust optimization of geometrical properties of flow diverter stents for treating cerebral aneurysm: A proof-of-concept study

This study presents a novel approach to optimize the design of flow diverter (FD) stents for cerebral aneurysm (CA) treatment. By addressing sources of uncertainty in cardiovascular simulations, including geometrical and physical properties and boundary conditions, we aim to assess the applicability of robust optimization techniques to the FD design, establishing a foundation for acquiring robust FDs that are capable of operating consistently under various real-world scenarios. Blood flow in a simplified 2-dimensional CA and FD model was simulated through computational fluid dynamics (CFD). A design space exploration method, incorporating Latin hypercube sampling and Kriging surrogate models, was employed to obtain the optimal solution. The objective was to maximize the reduction in velocity and vorticity within the CA sac. This study used non-intrusive polynomial chaos expansion (PCE) to quantify and propagate the input uncertainties through the computational model and compute the statistical moments of velocity and vorticity reductions. To assess the effect of uncertain sources on objective functions, a sensitivity analysis method based on Sobol indices was applied. Robust optimization involved simultaneously optimizing the mean and standard deviation of velocity reduction. Additionally, we accounted for patients’ specific conditions and repeated the robust optimization. The results indicate that blood Hematocrit and inlet velocity are the most impactful uncertain sources in FD optimization. Moreover, the obtained Pareto front shows that in robust designs, FD struts are concentrated in the distal region of the CA neck, while optimal designs have more struts in the proximal region. This study proposes an FD that compromises robustness and optimality with a velocity reduction of 72.31 % and a standard deviation of 0.00343.

Investigating Methods for ASPmT-Based Design Space Exploration in Evolutionary Product Design

Nowadays, product development is challenged by increasing system complexity and stringent time-to-market. To handle the demanding market requirements, knowledge from prior product generations is used to derive new, but partially similar product versions. The concept of product generation engineering, hence, allows manufacturers to release high-quality products within short development times. Therefore, in this paper, we propose a novel approach to evaluate the similarity of two product implementations based on the concept of the Hamming distance. This allows the usage of similarity information in various heuristics as well as in strategies and thus, to improve the product design process. In a wide set of cases, we investigate the quality and similarity of design points. In the experiments, the use of strategies leads to significantly short searching times, but also tends to be too restrictive in certain cases. Simultaneously, the quality of the solutions found in the heuristic design space exploration has been shown to be as good or better than for the search from scratch and considerably closer solutions as part of the non-dominated solution front have been found.

Automated design space exploration for poultry processing systems using discrete-event simulation

Abstract The poultry processing industry struggles to keep up with new developments in meat consumption and livestock breeding. Designing poultry processing systems is becoming increasingly more complex, and an increasing number of iterations of (re)design are required to optimize the product flow in these systems. To address this issue, this study presents a discrete-event simulation-based method for design space exploration of production systems. This method is mostly automated, greatly reducing the time and effort required in the design process. The steps that are automated are iterating on the design, model construction, performing simulation experiments, and interpreting the simulation results. An industrial case study in which a poultry processing system is redesigned is used to validate the effectiveness of the proposed method. A detailed description of this case study is given to showcase the different ways in which this design space exploration method can be used.

ACDSE: A Design Space Exploration Method for CNN Accelerator based on Adaptive Compression Mechanism

Customized accelerators for Convolutional Neural Network (CNN) can achieve better energy efficiency than general computing platforms. However, the design of a high-performance accelerator should take into account a variety of parameters and physical constraints. The increasing parameters and tighter constraints gradually complicate the design space, which poses new challenges to the capacity and efficiency of design space exploration methods. In this paper, we provide a novel design space exploration method named ACDSE for optimizing the design process of CNN accelerators. ACDSE implements the adaptive compression mechanism to dynamically adjust the search range and prune low-value design points according to the exploration states. As a result, it can focus on valuable subspace while also improving exploration capacity and efficiency. Additionally, we implement ACDSE to address the problem of CNN accelerator latency optimization. The experiment indicates that, compared to former DSE methods, ACDSE can reduce latency and increase efficiency by 1.39x-5.07x and 2.07x-43.87x, respectively, under the most stringent constraint conditions, demonstrating its superior adaptability to the complicated design space.

A similarity-assisted multi-fidelity approach to conceptual design space exploration

In conceptual design studies engineers typically utilize data-based surrogate models to enable rapid evaluation of design objectives that otherwise would be too computationally expensive and time-consuming to simulate. Due to the computationally expensive simulations, the data-based surrogate models are often trained using small sample sizes, resulting in low-fidelity models which can produce results that are not trustworthy. To mitigate this issue, a similarity-assisted design space exploration method is proposed. The similarity is measured between design points that have been evaluated through lower-fidelity data-based surrogate models and design points that have been evaluated using higher-fidelity physics-based simulations. This similarity information can then be used by design engineers to better understand the trustworthiness of the data produced by the low-fidelity surrogate models. Our numerical experiments demonstrate that such a similarity measurement can be used as an indicator of the trustworthiness of the lower-fidelity model predictions. Moreover, a second similarity metric is proposed for measuring the similarity of new designs to legacy designs, thus highlighting the potential to reuse knowledge, analysis models, and data. The proposed method is demonstrated by means of an aero-engine structural component conceptual design study. An open-source software tool developed to assist in data visualization is also presented.

Generative methods for Urban design and rapid solution space exploration

Rapid population growth and climate change drive urban renewal and urbanization at massive scales. New computational methods are needed to better support urban designers in developing sustainable, resilient, and livable urban environments. Urban design space exploration and multi-objective optimization of masterplans can be used to expedite planning while achieving better design outcomes by incorporating generative parametric modeling considering different stakeholder requirements and simulation-based performance feedback. However, a lack of generalizable and integrative methods for urban form generation that can be coupled with simulation and various design performance analysis constrains the extensibility of workflows. This research introduces an implementation of a tensor-field–based generative urban modeling toolkit that facilitates rapid design space exploration and multi-objective optimization by integrating with Rhino/Grasshopper ecosystem and its urban analysis and environmental performance simulation tools. Our tensor-field modeling method provides users with a generalized way to encode contextual constraints such as waterfront edges, terrain, view-axis, existing streets, landmarks, and non-geometric design inputs such as network directionality, desired densities of streets, amenities, buildings, and people as forces that modelers can weigh. This allows users to generate many, diverse urban fabric configurations that resemble real-world cities with very few model inputs. We present a case study to demonstrate the proposed framework's flexibility and applicability and show how modelers can identify design and environmental performance synergies that would be hard to find otherwise.

Design Space Exploration of Lithium-Ion Battery Packs for Hybrid-Electric Regional Aircraft Applications

Distributed hybrid and electric propulsion systems are one of the most promising technologies to reduce aircraft emissions, resulting in research efforts to investigate new architectures and the design of optimal energy management strategies. This work defines the optimal requirements in terms of battery pack sizing and cell technology for a hybrid-electric regional wing-mounted distributed propulsion aircraft through the application of a design space exploration method. The propulsion system considered in this study is a series-parallel hybrid turboelectric power train with distributed electric fans. A set of six lithium-ion battery cell technologies was identified and experimentally characterized, including both commercially available and prototype cells at different combinations of specific energy and power. A model of the aircraft was developed and used to define the optimal energy management strategy for the hybrid turboelectric propulsion system, which was solved using dynamic programming. The design space exploration was conducted by varying the cell technology and battery storage system size; and the effects on fuel consumption, energy management strategy, and thermal management were compared.

Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications

The widespread use of the internet of things (IoT) is due to the value of the data collected by IoT devices. These IoT devices generate, process, and exchange large amounts of safety-critical or privacy-sensitive data. Before transmission, the data should be protected against information leakage and data stealing. Deploying authenticated encryption with additional data (AEAD) algorithms on IoT devices ensures data confidentiality and integrity. However, AEAD algorithms are computationally intensive, while IoT devices are resource constrained or even battery powered. Therefore, a low-cost, low-power, and high-efficiency method of implementing an AEAD algorithm into resource-constrained IoT devices is required. The SM4-CCM algorithm, introduced in RFC 8998, is selected as the AEAD algorithm to address this problem. Algorithms similar to SM4-CCM (e.g., SM4 and AES-CCM) provide many architectural design references, but it is challenging to decide which architecture is the most suitable for SM4-CCM. In order to find the most efficient SM4-CCM hardware architecture, a design space exploration method is proposed. Firstly, the SM4-CCM algorithm is divided into five layers, and three candidate architectures are provided for each layer. Secondly, 63 design schemes for SM4-CCM are constructed by combining candidate architectures from each layer. Finally, a batch number of comparisons and analyses of experimental results are used to identify the most efficient one. Under TSMC 90 nm technology, the experimental results of the identified scheme show that the throughput, power consumption, and area achieve 199.99 Mbps, 1.625 mW, and 14.6 K gates, respectively. As a proof of concept, implementing this scheme on an FPGA board is also presented.

E/E Architecture Synthesis: Challenges and Technologies

In recent years, the electrical and/or electronic architecture of vehicles has been significantly evolving. The new generation of cars demands a considerable amount of computational power due to a large number of safety-critical applications and driver-assisted functionalities. Consequently, a high-performance computing unit is required to provide the demanded power and process these applications while, in this case, vehicle architecture moves toward a centralized architecture. Simultaneously, appropriate software architecture has to be defined to fulfill the needs of the main computing unit and functional safety requirements. However, the process of configuring and integrating critical applications into a vehicle central computer while meeting safety requirements and optimization objectives is a time-consuming, complicated, and error-prone process. In this paper, we firstly present the evolution of the vehicle architecture, past, present, and future, and its current bottlenecks and future key technologies. Then, challenges of software configuration and mapping for automotive systems are discussed. Accordingly, mapping techniques and optimization objectives for mapping tasks to multi-core processors using design space exploration method are studied. Moreover, the current technologies and frameworks regarding the vehicle architecture synthesis, model analysis with regard to software integration and configuration, and solving the mapping problem for automotive embedded systems are expressed. Finally, we propose four research questions as future works for this field of study.

Robustness guarantees for structured model reduction of dynamical systems with applications to biomolecular models

AbstractModel reduction methods usually focus on the error performance analysis; however, in presence of uncertainties, it is important to analyze the robustness properties of the error in model reduction as well. This problem is particularly relevant for engineered biological systems that need to function in a largely unknown and uncertain environment. We give robustness guarantees for structured model reduction of linear and nonlinear dynamical systems under parametric uncertainties. We consider a model reduction problem where the states in the reduced model are a strict subset of the states of the full model, and the dynamics for all of the other states are collapsed to zero (similar to quasi‐steady‐state approximation). We show two approaches to compute a robustness guarantee metric for any such model reduction—a direct linear analysis method for linear dynamics and a sensitivity analysis based approach that also works for nonlinear dynamics. Using the robustness guarantees with an error metric and an input‐output mapping metric, we propose an automated model reduction method to determine the best possible reduced model for a given detailed system model. We apply our method for the (1) design space exploration of a gene expression system that leads to a new mathematical model that accounts for the limited resources in the system and (2) model reduction of a population control circuit in bacterial cells.

A Cost-Efficient Data-Driven Approach to Design Space Exploration for Personalized Geometric Design in Additive Manufacturing

Abstract Additive manufacturing (AM) is considered as a key to personalized product realization as it provides great design flexibility. As the flexibility radically expands the design space, current design space exploration methods for personalized geometric designs become time-consuming due to the use of physically based computer simulations (e.g., finite element analysis or computational fluid dynamics). This poses a significant challenge in design for an efficient personalized product realization cycle, which imposes a tight computation cost constraint to timely respond to every new requirement. To address the challenge, we propose a cost-efficient data-driven design space exploration method for personalized geometric design in AM, enabling feasible design regions under the computation constraint. Specifically, the proposed method adopts surrogate modeling of efficient voxel model-based design rules to identify feasible design regions considering both manufacturability and personalized needs. Since design rules take much less time for evaluation than physically based simulations, the proposed method can contribute to timely providing feasible design regions for an efficient personalized product realization cycle. Moreover, we develop a cost-based experimental design for surrogate modeling, which enables the evaluation of additional design points to provide more precise feasible design regions under the computation cost constraint. The merits of the proposed method are elaborated via additively manufactured microbial fuel cell (MFC) anode design.

ERDSE: efficient reinforcement learning based design space exploration method for CNN accelerator on resource limited platform

Convolutional Neural Network (CNN) accelerator design on resource limited platform faces the challenge of lacking efficient design space exploration (DSE) method because of its huge and irregular design space. Numerous parameters belong to accelerator architecture and dataflow mode jointly construct a huge design space while power and resource constrains make the design space become quite irregular. Under such circumstances, traditional DSE methods based on exhaustive search is infeasible for the non-trivial design space and methods based on general optimization algorithms will also be inefficient because of the irregular distribution of design points. In this paper, we provide an efficient DSE method named ERDSE for CNN accelerator design on resource limited platform. ERDSE is based on reinforcement learning algorithm REINFORCE but refines it to adapt the complex design space. ERDSE implements off-policy strategy to decouple sampling and learning phase, then separately refines them to further improve exploration ability and samples utilization. We implement ERDSE to optimize the computing latency of CNN accelerator for VGG-16 and MobileNet-V3. Under the tightest constraints, ERDSE achieves 1.2x-1.7x (on VGG-16) and 2.3-4.9x (on MobileNet-V3) latency improvement compared with other DSE methods, which demonstrates the efficiency of ERDSE.

Cooperative Coevolution-based Design Space Exploration for Multi-mode Dataflow Mapping

Some signal processing and multimedia applications can be specified by synchronous dataflow (SDF) models. The problem of SDF mapping to a given set of heterogeneous processors has been known to be NP-hard and widely studied in the design automation field. However, modern embedded applications are becoming increasingly complex with dynamic behaviors changes over time. As a significant extension to the SDF, the multi-mode dataflow (MMDF) model has been proposed to specify such an application with a finite number of behaviors (or modes) and each behavior (mode) is represented by an SDF graph. The multiprocessor mapping of an MMDF is far more challenging as the design space increases with the number of modes. Instead of using traditional genetic algorithm (GA)-based design space exploration (DSE) method that encodes the design space as a whole, this article proposes a novel cooperative co-evolutionary genetic algorithm (CCGA)-based framework to efficiently explore the design space by a new problem-specific decomposition strategy in which the solutions of node mapping for each individual mode are assigned to an individual population. Besides, a problem-specific local search operator is introduced as a supplement to the global search of CCGA for further improving the search efficiency of the whole framework. Furthermore, a fitness approximation method and a hybrid fitness evaluation strategy are applied for reducing the time consumption of fitness evaluation significantly. The experimental studies demonstrate the advantage of the proposed DSE method over the previous GA-based method. The proposed method can obtain an optimization result with 2×−3× better quality using less (1/2−1/3) optimization time.

Design space exploration of optimized hybrid SVPWM techniques based on spatial region for three level VSI

The performance of a multilevel inverter depends upon design and selection of an appropriate modulation technique. Space vector pulse width modulation (SVPWM) technique offers more flexibility than other pulse width modulation (PWM) techniques. However, conventional SVPWM technique becomes more complex for multilevel inverter because of increased number of space vectors and redundant switching states. This paper presents a design space exploration method of hybrid SVPWM techniques for three level voltage source inverter (VSI) to reduce total harmonic distortion (THD) and switching loss over wide linear modulation range. A new parameter Harmonic Loss (product of weighted total harmonic distortion factor of the line voltage (Vwthd) and normalized switching loss) is introduced as an objective function, and a spatial region identification algorithm is proposed to determine the optimized switching sequences for hybrid SVPWM technique. Two optimized hybrid SVPWM techniques are proposed based on the optimized switching sequences for three level VSI. The proposed hybrid SVPWM techniques are implemented on a low cost PIC microcontroller (PIC 18F452) and applied on an experimental prototype of three phase three level VSI with an induction motor as load. The experimental results are demonstrated to validate the performance of the proposed hybrid SVPWM techniques.

Efficient field‐programmable gate array‐based reconfigurable accelerator for deep convolution neural network

Deep convolutional neural networks (DCNNs) have been widely applied in various modern artificial intelligence (AI) applications. DCNN's inference is a process with high calculation costs, which usually requires billions of multiply-accumulate operations. On mobile platforms such as embedded systems or robotics, an efficient implementation of DCNNs is significant. However, most previous field-programmable gate array-based works on accelerators for DCNNs just support one DCNN or just support convolution layers. In order to address this limitation, this work proposes a reconfigurable accelerator. The accelerator is flexible and can support multiple DCNNs and different layer types, such as convolution, pooling, activation function, and full connection layers. It is equipped with a five-level pipeline convolution engine whose main component is two processing element arrays. Furthermore, a design space exploration method is proposed to make full advantage of the proposed accelerator. This accelerator is implemented with the ZYNQ-7 ZC706 evaluation board and achieves a high performance of 53.29 Giga operations per second (GOPS) on AlexNet and 45.09 GOPS on YOLOv2-tiny at 100 MHz. Further performance of the accelerator is compared with the previous works, and it achieves multiple advantages: High performance, high configurability, and efficient resource utilisation.

Design Space Exploration for an IoT Node: Trade-Offs in Processing and Communication

The proliferation of smart sensor nodes for IoT deployments comes with requirements of energy efficiency and to fulfil functional requirements, but it also demands a fast time to market. As a result, we need to facilitate the design of these IoT nodes, while providing the required performance. In this article, we introduce a design space exploration method focusing on IoT nodes that are data intensive due to the inherent complexity of their high data volume. The proposed method aims to identify areas of the design where processing optimisation would have a greater impact on the overall node energy consumption, define an energy budget for prospective additional tasks in the processing pipeline, and in conclusion evaluate the optimal node offloading configuration.

Hardware architecture exploration: automatic exploration of distributed automotive hardware architectures

As the engineering of distributed embedded systems is getting more and more complex, due to increasingly sophisticated functionalities demanding more and more powerful hardware, model-based development of software-intensive embedded systems has become a de facto standard in recent years. Among other advantages, it enables design space exploration methods allowing for frontloading techniques which support a system architect already at early stages of development. In this paper, we want to present an approach which is capable of automatically generating automotive E/E architectures (electric/electronic architecture; in-car network of processing units and buses). Based on the concept of viewpoints, we will introduce dedicated technical meta-models, a language to formally describe a hardware architecture exploration problem and an automatic exploration approach using satisfiability modulo theories. We will furthermore introduce a dedicated methodology and show how an exploration integrates into a system development process. In the end, we will evaluate our approach by applying it to an industrial use case provided by Continental.

Mapping the design space in function and geometry models supporting redesign for additive manufacturing

The advent of additive manufacturing (AM) brings many benefits in terms of lightweight design. However, there is no established design for additive manufacturing (DfAM) method available, nor are all the impacts and constraints on the product and development process known. Therefore, a method to redesign existing products for AM is proposed. It consists of functional decomposition enhanced by constraints identification, and analyses of the impact on the design space. Furthermore, the approach defines a coupling of function and geometry models to support an inter-domain redesign process. The approach has been successfully applied in an industrial collaboration project with three aerospace companies, where the support of the method for design space exploration has been recognised. Future work sees the use of this method for design space exploration even outside the AM domain, but a more methodical definition of the relationship between the functional and geometrical domain is required to do so.

Mapping the design space in function and geometry models supporting redesign for additive manufacturing

The advent of additive manufacturing (AM) brings many benefits in terms of lightweight design. However, there is no established design for additive manufacturing (DfAM) method available, nor are all the impacts and constraints on the product and development process known. Therefore, a method to redesign existing products for AM is proposed. It consists of functional decomposition enhanced by constraints identification, and analyses of the impact on the design space. Furthermore, the approach defines a coupling of function and geometry models to support an inter-domain redesign process. The approach has been successfully applied in an industrial collaboration project with three aerospace companies, where the support of the method for design space exploration has been recognised. Future work sees the use of this method for design space exploration even outside the AM domain, but a more methodical definition of the relationship between the functional and geometrical domain is required to do so.

Improving HW/SW Adaptability for Accelerating CNNs on FPGAs through A Dynamic/Static Co-Reconfiguration Approach

With the continuous evolution of Convolutional Neural Networks (CNNs) and the improvement of the computing capability of FPGAs, the deployment of CNN accelerator based on FPGA has become more and more popular in various computing scenarios. The key element of implementing these accelerators is to take full advantage of underlying hardware characteristics to adapt to the computational features of the software-level CNN model. To achieve this goal, however, previous designs mainly focus on the static hardware reconfiguration pattern, which is not flexible enough and can hardly make the accelerator architecture and the CNN features fully fit, resulting in inefficient computations and data communications. By leveraging the dynamic partial reconfiguration technology equipped in the modern FPGA devices, in this article, we propose a new accelerator architecture for implementing CNNs on FPGAs in which static and dynamic reconfigurabilities of the hardware are cooperatively utilized to maximize the acceleration efficiency. Based on this architecture, we further present a systematic design and optimization methodology for implementing the specific CNN model in the particular computing scenario, in which a static design space exploration method and a reinforcement learning-based decision method are proposed to obtain the optimal static hardware configuration and run-time reconfiguration strategy respectively. We evaluate our proposal by implementing three widely used CNN models, AlexNet, VGG16C, and ResNet34, on the Xilinx ZCU102 FPGA platform. Experimental results show that our implementations on average can achieve 683 GOPS under 16-bit fixed data type and 1.37 TOPS under 8-bit fixed data type for three targeted CNN models, and improve the computational density from 1.1× to 1.91× compared with previous implementations on the same type of FPGA platform.