Design Of Tunnel Field Effect Transistor Research Articles

Tunneling towards efficiency: A survey of design and optimization strategies for tunnel FETs in ultra-low power applications

The tunnel field-effect transistor (TFET) is a promising technology for low-power applications due to its high performance at reduced voltages through quantum tunneling. This article overviews TFETs and their potential to reduce power consumption in digital circuits, analog circuits, and energy harvesting applications. It highlights the challenges faced in TFET design, including gate electrostatics, source doping, and off-state limitations. The importance of design considerations and material selections is discussed, emphasizing their impact on TFET performance. Various fabrication techniques for TFETs are explored, highlighting their significance in achieving efficient and effective devices. The review concludes by stressing the need for further research and development to address existing challenges and unlock the full potential of TFETs in low-power electronic systems.

Graphene antidot nanoribbon tunnel field‐effect transistor

A graphene nanoribbon tunnel field-effect transistor (TFET) model is proposed, in which the antidot pattern is used to generate the heterojunction (HJ) band structure. The intrinsic strain at the HJ interface is absent naturally, greatly avoiding the tunnelling blocking effect of the interface states. The energy gap (Eg) of the graphene antidot nanoribbon (GANR) can be flexibly modulated through the antidot morphology, resulting in highly tunable device performance. Moreover, the stability of the TFET behaviours considering the patterning technology issue is studied. Simulation results indicate that the GANR is suitable for the TFET design in different application scenarios.

Tunnel Field Effect Transistor Design and Analysis for Biosensing Applications

Tunnel Field Effect Transistor Design and Analysis for Biosensing Applications

Analysis of Hetero-Stacked Source TFET and Heterostructure Vertical TFET as Dielectrically Modulated Label-Free Biosensors

This paper reports an extensive comparison of a hetero-stacked source tunnel field effect transistor (TFET) and heterostructure vertical TFET as label-free biosensors based on dielectric modulation. Due to the difference in the TFET design, the vertical TFET possess highrer sensitivity, ON-state current, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{ON}/\text{I}_{OFF}$ </tex-math></inline-formula> ratio and a lower subthreshold swing. Comparative analysis is carried out using technology computer aided design (TCAD) simulator where the sensitivity of the biosensors has been studied taking into consideration neutral and charged biomolecules for various dielectric constant values. Study of the phenomenon of steric hindrances and probe irregular placements provide better understanding of non-ideal state of the sensors. Due to the structural differences between the biosensors, decreasing step profile exhibits the highest sensitivity for hetero-stacked source TFET biosensor whereas increasing step profile shows the highest sensitivity for heterostructure vertical TFET biosensor. For a particular dielectric constant value of the biomolecule, the vertical based TFET biosensor is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> times higher in terms of sensitivity as compared to the hetero-stacked source TFET biosensor when considering steric hindrances. Finally, the biosensors are benchmarked against other published literatures and it shows that the sensitivity of the heterostructure vertical TFET biosensor is overall higher than other FET based biosensors.

Optimization and Performance Prediction of Tunnel Field‐Effect Transistors Based on Deep Learning

AbstractThe tunnel field‐effect transistor (TFET) is considered to be a suitable substitute for metal oxide semiconductor‐field effect transistors in the post‐“Moore's Law” era owing to its low power consumption. However, Si‐TFETs face the drawbacks of low on‐state currents and significant ambipolar leakage. This study proposes a GeSi/Si heterojunction double‐gate TFET with a T‐channel hetero‐gate dielectric (HJ‐HGD‐DGTFET) structure to overcome these problems. It also presents a novel method of predicting and optimizing the performance of the existing TFETs which use deep learning to accelerate the device design. Furthermore, this study proposes a neural network based on different requirements to perform two functions: prediction of the device performance using the forward design, and the forecast of the device structure using the inverse design. It can thus be used to determine whether the output of the network meets the design objectives and if it is necessary to change the output by adjusting the input, and lastly achieve the TFET performance prediction and device optimization. The proposed method can be used to design TFETs accurately and efficiently even without professional knowledge. This study provides guidance for the design and optimization of TFETs along with other microelectronic devices.

Design of TFET based Op-Amp and CCII for low voltage and low power applications

ABSTRACT This paper presents design of an ultra-low-power two-stage Op-Amp and Second-generation current conveyor (CCII) using gm/ technique for portable applications like biomedical instruments, wireless sensor networks (WSNs), etc. The designed circuits are based on 20 m Tunnel Field-Effect Transistor (TFET). The circuits use a single power supply of 0.9 V and provide improvements in many areas when compared with Carbon Nanotube FET (CNTFET) based circuits and existing TFET-based circuits. The simulation set up in HSPICE, provide very low-power consumption for the same performanceand provide much better performance for the same power consumption when compared with existing circuits. In the case of TFET-based Op-Amp, for the power consumption of 47.1 W, the GBW and open-loop DC gain are 5.12 MHz and 75.9 dB, respectively. While for the power consumption of 107.1 W, the GBW and open-loop DC gain are 9.01 MHz and 74.9 dB, respectively. In case of TFET-based CCII, for the power consumption of 82.3 W, the 3-dB BW for Voltage and Current transfer gains are 700 MHz and 135 MHz, respectively. While for the power consumption of 173 W, the 3-dB BW for Voltage and Current transfer gains are 1.12 GHz and 226 MHz respectively.

Device physics and design of symmetrically doped tunnel field-effect transistors

Symmetric tunnel field-effect transistors (TFETs) have recently been proposed in order to make the design and fabrication of TFET-based circuits favorable. In this paper, we adequately investigate the device physics and design of point-tunneling TFETs with symmetric doping profiles. Based on two-dimensional numerical simulations, it is shown in the proposed symmetric TFETs that the on-current is doubled due to an additional source and the ambipolar off-leakage is significantly diminished because the drain tunnel junction is designed far from the gate. Moreover, those advantages in on- and ambipolar off-currents are not only performed in high-bandgap but also remained in low-bandgap materials. Examining the roles of structure parameters indicates that designing the drain junction width, the gate, drain-to-gate or horizontal drain-to-source lengths smaller than their lower limits, namely in this investigation, 20, 80, 70 and 20 nm, respectively, can severely deteriorate the on- and/or off-currents of the normal symmetric TFETs. Based on the design guidelines provided, an advanced Y-shaped structure is proposed to simultaneously optimize both the electrical characteristics and the scalability of symmetrically doped TFETs.

Performance improvement of doped TFET by using plasma formation concept

Formation of abrupt doping profile at tunneling junction for the nanoscale tunnel field effect transistor (TFET) is a critical issue for attaining improved electrical behaviour. The realization of abrupt doping profile is more difficult in the case of physically doped TFETs due to material solubility limit. In this concern, we propose a novel design of TFET. For this, P+ (source)-I (channel)-N (drain) type structure has been considered, wherein a metal electrode is deposited over the source region. In addition to this, a negative voltage is applied to the source electrode (SE). It induces the surface plasma layer of holes in the source region, which is responsible for steepness in the bands at source/channel junction and provides the advantage of higher doping in source region without any addition of the physical impurity. The proposed modification is helpful for achieving steeper band bending at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface and overcomes the issue of low ON-state current. Thus, the proposed device shows the increment of 2 decades in drain current and 252 mV reduction in threshold voltage compared with conventional device. The optimization of spacer length (LSG) between source/gate (LSG) and applied negative voltage (Vpg) over source electrode have been performed to obtain optimum drain current and threshold voltage (Vth). Further, for the suppression of ambipolar current, drain region is kept lightly doped, which reduces the ambipolar current up to level of Off state current. Moreover, in the proposed device gate electrode is underlapped for improving RF performance. It also reduces gate to drain capacitances (Cgd) and increases cut-off-frequency (fT), fmax, GBP, TFP. In addition to these, linearity analysis has been performed to validate the applicability of the device.

Impact of gate leakage considerations in tunnel field effect transistor design

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-κ gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods for reducing the gate leakage, we show that if the gate tunneling leakage is not considered, even for these two methods, the overall TFET off-state current will be significantly underestimated. Our results demonstrate the need to carefully account for the gate leakage in the design of TFETs just as it is done for the conventional nanoscale MOSFETs.

Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors

The low-bandgap engineering and line-tunneling architecture are the two major techniques to resolve the ON-current issues of tunnel field-effect transistors (TFETs). This paper elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. Three semiconductors, Ge, InAs, and InSb, are considered as examples to explore their physical operations and analytical models. 2-D device simulations were performed to examine the on/off characteristics. The appropriate operational voltages depend on the associated bandgap of semiconductors. The gate voltage should be larger than the bandgap voltage (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> /q) to ensure high ON-currents, whereas the drain voltage must be less than the bandgap voltage to control OFF-leakages. Because the minimum tunnel path has a key function in determining the tunneling in line-tunneling TFETs, the tunneling current is reformulated in terms of the minimum tunnel path with friendly compact forms. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs.