Single Photon Avalanche Diode Design Research Articles

CMOS Single-Photon Avalanche Diode Circuits for Probabilistic Computing.

Intrinsically random hardware devices are increasingly attracting attention for their potential use in probabilistic computing architectures. One such device is the single-photon avalanche diode (SPAD) and an associated functional unit, the variable-rate SPAD circuit (VRSC), recently proposed by us as a source of randomness for sampling and annealing Ising and Potts models. This work develops a more advanced understanding of these VRSCs by introducing several VRSC design options and studying their tradeoffs as implemented in a 65-nm CMOS process. Each VRSC is composed of a SPAD and a processing circuit. Combinations of three different SPAD designs and three different types of processing circuits were evaluated on several metrics such as area, speed, and variability. Measured results from the SPAD design space show that even extremely small SPADs are suitable for probabilistic computing purposes, and that high dark count rates are not detrimental either, so SPADs for probabilistic computing are actually easier to integrate in standard CMOS processes. Results from the circuit design space show that the time-to-analog-based designs introduced in this work can produce highly exponential and analytical transfer functions, but that the less analytically tractable output of the previously proposed filter-based designs can achieve less variability in a smaller footprint. Probabilistic bits (P-bits) composed of the fabricated VRSCs achieve bit flip rates of 50 MHz and allow at least one order of magnitude of control over their simulated annealing temperature.

3D Simple Monte Carlo Statistical Model for GaAs Nanowire Single Photon Avalanche Diode

GaAs based nanowire single photon avalanche diode (SPAD) has been demonstrated with extremely small afterpulsing probability and low dark count rate, and hence it has attracted wide attention for the near infrared applications. However, there is a lack of model to accurately evaluate the avalanche breakdown performance in nanowire SPAD with a spatially non-uniform electric field. In this work, we have developed a three-dimensional (3D) Simple Monte Carlo statistical model for GaAs nanowire SPADs. Model validation includes ionisation coefficients of GaAs and avalanche gain in GaAs nanowire avalanche photodiode. We also apply our model to predict the device performances of breakdown probability, mean time to breakdown and timing jitter, which are essential parameters for SPAD design. Simulating a PN junction GaAs nanowire SPAD design using our model, we found that device performances have little dependence on the primary carrier injection type, but the nanowire doping concentration requires optimization for high performance SPAD design and operation.

Microscale mapping of SPAD photon detection probability

As silicon photomultiplier (SiPM) technology still has potential for further improvements, we describe a method to map the photon detection probability of a single-photon avalanche diode (SPAD) at the microscale level, in order to evaluate the behavior of the SPAD triggering capabilities as a function of the position of the incident light and to determine its homogeneity. For this purpose, we performed the analysis of the light response for a single active SPAD, with all its neighbors switched off, using a scanning setup, composed of the digital SiPM SPADnet-I data acquisition system, a microscope, a servo positioning system, a spectrograph and a CCD camera. We varied the wavelength of the incoming light to probe the device volume from the P-well to the N-well, with the ultimate goal of understanding and improving overall sensor performance. The comparison of this study to SPAD design and electric field technology computer-aided design (TCAD) simulation enables one to estimate how much the P-well drawn area could be increased to optimize fill factor without causing premature edge breakdown through guard ring failure.

Implementation Study of Single Photon Avalanche Diodes (SPAD) in <formula formulatype="inline"><tex Notation="TeX">$0.8~\mu\hbox{m}$</tex> </formula> HV CMOS Technology

Single Photon Avalanche Diodes (SPAD) are known for their excellent timing performance which enables Time of Flight capabilities in positron emission tomography (PET). However, current array architectures juxtapose the SPAD with its ancillary electronics at the expense of a poor fill factor of the SPAD array. The 3D vertical integration of SPADs and readout electronics represents a solution to the aforementioned problem. Compared to systems with external electronics readout, 3D vertical integration reduces the SPAD interconnect parasitic capacitance while greatly increasing the photosensitive area and improving overall performances. This paper presents the implementation of two SPAD structures designed for PET. The SPAD structures are designed using Teledyne DALSA high voltage (HV) CMOS technology targeted for a 3-dimensional single photon counting module (3DSPCM). SPAD with two types of guard ring (diffusion-based and virtual guard ring) are designed, fabricated and characterized. All structures are based on a $p + $ anode in an $n$ -well cathode and are implemented along with active quenching circuits for proper characterization. The results show that the contact distribution and the anode-cathode spacing impact the dark count rate (DCR). The design of SPADs with a diffusion guard ring have a DCR down to $3~\hbox{s}^{- 1}\mu \hbox{m}^{-2}$ at room temperature, afterpulsing probability of $ , timing resolution of 27 ps FWHM and PDE of 49% at 480 nm.

Characterization of Single Photon Avalanche Diodes Fabricated by 0.13μm Flash Process Technology

Two different structures of single photon avalanche diode(SPAD) fabricated by 0.13 μm flash process technology are presented. The structure-1 uses low implanted p-well surrounding the active area as the guard ring which prevents the periphery breakdown, while for the structure-2, a virtual guard ring with the deep retrograde n-well doping is designed. The characteristics of the two detectors with the same active area diameter are presented. The two SPAD structures exhibit relatively different dark and light performance. The first structure exhibits a typical dark count rate of 18 kHz at the room temperature and a maximum photon detection efficiency of 15%, while the second structure exhibits a dark count rate of 23 kHz and a maximum photon detection efficiency of 28%. The comparison of the two structures is therefore promising for the further advanced SPAD design.

Fully-integrated CMOS single photon counter

Traditionally, Single Photon Avalanche Diodes (SPADs) are fabricated using dedicated processes that require additional technological steps when compared to standard CMOS. Instead, this paper presents the design of SPADs that attain good performances, by using a standard high-voltage CMOS process. The detector is monolithically integrated together with an Active Quenching Circuit (iAQC), a counter, and a serial communication interface. This opens the way to the design and fabrication of ultra compact multi-channel single-photon counters.