Design Of Random Number Generator Research Articles

New class of chaotic systems with equilibrium points like a three-leaved clover

This paper presents a new class of chaotic systems with infinite number of equilibrium points like a three-leaved clover. They signify an exciting class of dynamical systems which represent many major characteristics of regular and chaotic motions. These chaotic systems belong to the general class of chaotic systems with hidden attractors. By using a systematic computer search, three chaotic systems with three-leaved-clover-shaped equilibria were found which are classified into dissipative systems. Dynamics of the chaotic system with the three-leaved-clover-equilibria has been investigated by using phase portraits, bifurcation diagram, Lyapunov exponents, Kaplan–Yorke dimension and Poincare map. Moreover, an electronic circuit implementation of the theoretical system is designed to check its effectiveness. Random number generator design has been realized with newly developed chaotic systems. The obtained random bit sequences are used for image encryption. Security analysis of image encryption processes has been performed.

On the design of henon and logistic map-based random number generator

The key sequence is one of the main elements in the cryptosystem. True Random Number Generators (TRNG) method is one of the approaches to generating the key sequence. The randomness source of the TRNG divided into three main groups, i.e. electrical noise based, jitter based and chaos based. The chaos based utilizes a non-linear dynamic system (continuous time or discrete time) as an entropy source. In this study, a new design of TRNG based on discrete time chaotic system is proposed, which is then simulated in LabVIEW. The principle of the design consists of combining 2D and 1D chaotic systems. A mathematical model is implemented for numerical simulations. We used comparator process as a harvester method to obtain the series of random bits. Without any post processing, the proposed design generated random bit sequence with high entropy value and passed all NIST 800.22 statistical tests.

Design of efficient CMOS ring oscillator-based random number generator

ABSTRACTAlthough studies have investigated the effects of flicker noise on randomness, such effects demand further examination. Despite the random nature of flicker noise, a coloured distribution is observed in the power spectral density of flicker noise, indicating to a correlation in between adjacent samples. Studies have employed ring oscillators (ROs) that produce random numbers by sampling the digitised analogue signals of their outputs. This sampling procedure may change the spectral properties of flicker noise resulting from the folding effect of noise. Another topic of interest regarding sampled flicker noise is its random behaviour. To investigate the contribution of flicker noise, white noise, and their combination to randomness, we produce synthetic bit streams of these noise sources. From observations, we find that flicker noise contributes to the entropy of bit streams. Using the generated synthetic bit streams, we also explore the entropy dependence of a bit stream on the sampling period and analyse and compare the entropy levels of the outputs of ROs operating in strong and weak inversion. Results of the comparison demonstrate that only one RO operating in weak inversion may be sufficient to attain the required entropy level for qualifying the generated bit stream as random. The results of the analysis are also confirmed by measurements. In addition, the paper proposes an efficient design of a RO-based random number generator.

Design of high-throughput and low-power true random number generator utilizing perpendicularly magnetized voltage-controlled magnetic tunnel junction

A true random number generator based on perpendicularly magnetized voltage-controlled magnetic tunnel junction devices (MRNG) is presented. Unlike MTJs used in memory applications where a stable bit is needed to store information, in this work, the MTJ is intentionally designed with small perpendicular magnetic anisotropy (PMA). This allows one to take advantage of the thermally activated fluctuations of its free layer as a stochastic noise source. Furthermore, we take advantage of the voltage dependence of anisotropy to temporarily change the MTJ state into an unstable state when a voltage is applied. Since the MTJ has two energetically stable states, the final state is randomly chosen by thermal fluctuation. The voltage controlled magnetic anisotropy (VCMA) effect is used to generate the metastable state of the MTJ by lowering its energy barrier. The proposed MRNG achieves a high throughput (32 Gbps) by implementing a 64×64 MTJ array into CMOS circuits and executing operations in a parallel manner. Furthermore, the circuit consumes very low energy to generate a random bit (31.5 fJ/bit) due to the high energy efficiency of the voltage-controlled MTJ switching.

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The design and realization of a new high speed FPGA-based chaotic true random number generator

Chaotic systems and chaos-based applications have been commonly used in the fields of engineering recently. The most essential part of them is the chaotic oscillator that has very critical role in some applications such as chaotic communications and cryptography. In this study, Sundarapandian–Pehlivan chaotic system has been modeled and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. In the first stage, the chaotic system has been modeled numerically by the help of fourth order of Runge–Kutta (RK4) method. Additionally, phase portraits of the system have been obtained and Lyapunov exponents have been examined. Secondly, the system has been modeled by using PSpice for the implementation of the chaotic system with analog circuit elements. Then, Pspice simulation results have been compared with the numerical outcome to justify the designed model. Furthermore, the chaotic system has been physically confirmed with real analog circuit elements. Signals obtained from the physical system have been verified with both numerical and PSpice results. It has been also modeled by the help of method of RK4 in a hardware description language (VHDL) and the model further has been synthesized and tested for Xilinx Virtex-6 FPGA chip. Finally, the chaotic oscillator designed has been tested for True Random Number Generators (TRNG) and the maximum operating frequency has been achieved as 293MHz with a speed of 58.76Mbit/s. Besides, the random bit sets produced by TRNG have been further verified by FIPS-140-1 and NIST-800-22 statistical standards and it has been proved that the proposed design can be used in embedded cryptologic applications.

A New Approach to Analysis and Design of Chaos-Based Random Number Generators Using Algorithmic Converter

This paper presents a new approach to analysis and design of ADC-based random number generators. To this end, different full-bit and half-bit redundant stages of algorithmic converter are used to design chaotic maps. It is shown that, in the redundant and nonredundant structures, output probability density function of the converter stages and their related chaotic functions always converge to uniformity. It is demonstrated that residues become independent and uniformly distributed. This fact leads to the randomness and uniformity of distribution of the random number generator output bits. Moreover, it is shown that some common chaotic maps that are employed in chaotic random number generators can be implemented using nonredundant and half-bit redundant stages of algorithmic converter. In this way, the capability of ADC-based generators in designing chaotic maps and producing random number sequences is illustrated. The validity of the proposed chaos-based random number generator is confirmed using NIST statistical tests even in the presence of nonidealities in algorithmic converter. Since the ADCs are mixed-signal integrated circuits and can be used in high-speed applications, the ADC-based random number generator has high throughput and is easily embeddable in all analog and digital circuits.

Robust PRNG based on homogeneously distributed chaotic dynamics

This paper is devoted to the design of new chaotic Pseudo Random Number Generator (CPRNG). Exploring several topologies of network of 1-D coupled chaotic mapping, we focus first on two dimensional networks. Two topologically coupled maps are studied: TTLrc non-alternate, and TTLSC alternate. The primary idea of the novel maps has been based on an original coupling of the tent and logistic maps to achieve excellent random properties and homogeneous /uniform/ density in the phase plane, thus guaranteeing maximum security when used for chaos base cryptography. In this aim two new nonlinear CPRNG: MTTL2sc and NTTL2 are proposed. The maps successfully passed numerous statistical, graphical and numerical tests, due to proposed ring coupling and injection mechanisms.

Design and validation of high speed true random number generators based on prime-length ring oscillators

This paper presents a wide supply voltage range, high speed true random number generator (TRNG) based on ring oscillators, which have different prime number of inverters. And a simple Von Neumann corrector as post processing is also realized to improve data randomness. Prototypes have been implemented and fabricated in 0.18 µm complementary metal oxide semiconductor (CMOS) technology with a wide range of supply voltage from 1.8 V to 3.6 V. The circuit occupies 4 500 µm2, and dissipates minimum 160 µW of power with sampling frequency of 20 MHz. Output bit rate range is from 100 kbit/s to 20 Mbit/s. Statistical test results, which were achieved from the dieHard battery of tests, demonstrate that output random numbers have a well characteristic of randomness.

Minimalist design of a robust real-time quantum random number generator

We present a simple and robust construction of a real-time quantum random number generator (QRNG). Our minimalist approach ensures stable operation of the device as well as its simple and straightforward hardware implementation as a stand-alone module. As a source of randomness the device uses measurements of time intervals between clicks of a single-photon detector. The obtained raw sequence is then filtered and processed by a deterministic randomness extractor, which is realized as a look-up table. This enables high speed on-the-fly processing without the need of extensive computations. The overall performance of the device is around 1 random bit per detector click, resulting in 1.2 Mbit/s generation rate in our implementation.

A Physical Principle for Fast and Miniature Random Number Hardware Generator Using MPPC Photo Detector

This paper presents the physical concept and test results of sample data of the high-speed hardware true random number generator design based on typically used for High Energy Physics hardware. Main features of this concept are the high speed of the true random numbers generation (tens of Mbt/s), miniature size and estimated lower production cost. This allows the use of such a device not only in large companies and government offices but for the end-user data cryptography, in classrooms, in scientific Monte-Carlo simulations, computer games and any other place where large number of true random numbers is required. The physics of the operations principle of using a Geiger-mode avalanche photo detector is discussed and the high quality of the data collected is demonstrated.

A New Construction of Pseudorandom Number Generator

Random number sequences and RNGs play an important role in trusted computing environments and cryptographic applications. For example, we use random numbers in the generation of keys in TPM. In some web protocols, random numbers are applied to resist replay attacks. It is necessary to guarantee the quality of RNGs and their random sequences because deterministic factors are likely to be involved in the generation process. If a random number generator is not designed carefully, then the output number sequences may become predictable and bring high security risks. Thus, the design of random number generators that produce high-quality random number sequences has been a hot research topic in these decades. Recently, with the development of resource constrained environments, the demand of lightweight random number generators dramatically increases. People prefer to use the random number generators with extreme high efficiency in the on-the-fly applications. This will affect the security performance of the generators. In this paper, we design a random number generator which meets the current lightweight requirements in the resource-limited environments. Our design is originally based on a lightweight block cipher, and applies the property of random looking output of block cipher to the random number generators. We combine a traditional encryption mode with a novel structure for the random number generator, so that the trade-off between security and efficiency can be made perfectly. We also take a comprehensive security evaluation for our random number generator.

Architectural Design of Random Number Generators and Their Hardware Implementations

Architectural Design of Random Number Generators and Their Hardware Implementations

A noise-based IC random number generator for applications in cryptography

The design of a mixed-signal random number generator (RNG) integrated circuit (IC) suitable for integration with hardware cryptographic systems is presented. Certain applications in cryptography require the use of a truly RNG, a device which produces unpredictable and unbiased digital signals derived from a fundamental noise mechanism. For IC-based cryptographic systems, an RNG must harness randomness from a low-power noise signal yet remain insensitive to deterministic influences such as crosstalk, power supply noise, and clock signal coupling through the substrate. An RNG IC utilizing established analog IC design techniques was designed and fabricated in a 2-/spl mu/m CMOS technology. Sequences generated by the experimental system repeatedly passed many standard randomness tests for bit rates up to 1.4 MHz. No changes in randomness performance were observed as the system was exposed to power supply noise and substrate signal coupling. The system occupies a total chip area of 1.5 mm/sup 2/ and dissipates 3.9 mW of power.

Randomness By Design

Anyone who considers arithmetical methods of producing random digits is, of course, in a state of sin. I John von Neumann's famous dictum points an accusing finger at all who set their ordered minds to engender disorder. Much as in times past thieves, pimps, and actors carried on their profession with an uneasy conscience, so in this day scientists who devise random number generators suffer pangs of guilt. George Marsaglia, perhaps the preeminent worker in the field, quips when he asks his colleagues, Who among us has not sinned? Marsaglia's work at the Supercomputer Computations Research Institute at Florida State University is well-known. Inasmuch as Marsaglia's design and testing of random number generators depends on computation, and inasmuch as computation is fundamentally arithmetical, Marsaglia is by von Neumann's own account a sinner. Working as he does on a supercomputer, Marsaglia is in fact a gross sinner. This he freely admits. Writing of the best random number generators he is aware of, Marsaglia states, they are the result of arithmetic methods and those using them must, as all sinners must, face Redemption [sic] Day. But perhaps with better understanding we can postpone it. 2 Despite the danger of being branded a heretic, I want to argue that randomness entails no moral deficiency. I will even advocate that random number generators be constructed with reckless abandon-though a reckless abandon that is well thought out. Randomness, properly to be randomness, must leave nothing to chance. It must look like chance, like a child of the primeval chaos. But underneath a keen intelligence must be manipulating and calculating, taking advantage of this and that expedient so as systematically to concoct confusion. I am reminded of the photo-journalists in Viet-

Theory and design of a digital stochastic computer random number generator

The theory and design of a random number generator suitable for use in a general purpose digital stochastic computer is considered. After a review of possible types of random number generator the paper considers the design of a system for the generation of negatively correlated pseudo-random binary sequences. Specifically it is shown that the use of correlated sequences reduces the adverse effects of pure randomness whilst retaining the property of zero correlation between sequences fundamental to the theory of stochastic computation.