Quantum-dot Cellular Automata Design Research Articles

Reversible Palm Vein Authenticator Design With Quantum Dot Cellular Automata for Information Security in Nanocommunication Network

Palm vein pattern recognition is one of the most promising and rapidly developing fields of study in biometrics, which makes it an important solution for identity security in biometrics-based user identification systems. Quantum-dot Cellular Automata (QCA) is a developing field of nanotechnology which facilitates the creation of nano-scale logical circuits. Irreversible technology has faced some difficulties, such as higher heat energy dissipation. Reversible logic is therefore essential where heat dissipation is almost insignificant. This article proposes QCA design of a reversible circuit for palm vein authentication utilizing the Feynman gate. Fully reversible Feynman gate is designed. Using this newly designed Feynman gate the palm vein authenticator circuit is designed. The theoretical values and the results of the simulation correspond to the reliability of the planned circuit. Circuit complexity and circuit cost are explored. Validation of authenticated users by the proposed authenticator explores its design accuracy as per theoretical values. Energy dissipation of the proposed designs shows that it remains within Lauderer’s limit (0.06meV). This proves that the circuits designed are fully reversible in nature and dissipates very less amount of energy. Comparison with recent QCA state of the art architectures explores its characteristics.

Synchronization in Quantum-Dot Cellular Automata Circuits and Systems

Signal synchronization of large scale Quantum-dot Cellular Automata (QCA) circuits is one of the most complex QCA design challenges. More specifically, the QCA circuits synchronization problem, especially in the large circuits, is characterized as rather complex due to technology constraints. In this paper, by extensively analyzing the most important properties of the signal synchronization problem in QCA circuits, we propose an efficient design methodology to tackle the problem, based on the well-known from computer science, Firing Squad Synchronization Problem (FSSP). Comparing FSSP with the QCA circuits synchronization problem many similarities can be found. Among the numerous FSSP's algorithmic solutions in literature, the Mazoyer algorithm has proven to be the most efficient one. In this paper, a novel design and implementation in QCA technology of this algorithm is presented. Moreover, by the appropriate modification of the Mazoyer algorithm, we are able to propose a generic synchronization design methodology for QCA circuits and systems. This method is enhanced by a novel freezing technique, that makes it applicable to any QCA circuit and system as manifested by our corresponding simulation results. The proposed synchronization methodology is a universal design tool, that can be applied to exiting designs without increasing the complexity.

Effective RCA design using quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is a transistor less technology alternative to CMOS for developing low-power, high speed digital circuits. Adder circuits are broadly employed in all digital computation systems. In this paper, a novel coplanar QCA full adder circuit is proposed which is designed with minimum number of QCA cells. The proposed full adder requires only 13 QCA cells, an area of 0.008 μm2 and delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder (RCA) is designed based on the proposed full adder that performs higher end addition in an effective way. Simulations results are obtained precisely using QCA designer tool version 2.0.3. Also the simulation results shows that the proposed 4-bit Ripple Carry Adder (RCA) requires only 70 QCA cells, an area of 0.18 μm2 and delay of about 5 clock cycles to implement its function with enhanced performance in terms of latency, area and QCA Cost. From the comparisons, it is found that our work achieves over 55% improvement in QCA cell count.

Efficient design of QCA based hybrid multiplier using clock zone based crossover

Quantum-dot cellular automata (QCA) is an emerging trend in nanotechnology and appropriate for the development of high performance and low power integrated circuit design. Dadda and Wallace tree multipliers are designed by employing CZBCO technique to overcome the crossover issues of geometric design complexity and alignment accuracy and also to achieve high device density. The proposed design of QCA-based Hybrid parallel multiplier consists of decomposing structure that adopts Dadda and Wallace algorithms to optimize the design. In this proposal, N-bit multiplier array is decomposed into four N/2-bit multiplier arrays that are easily constructed by employing both Wallace and Dadda multipliers. The Hybrid multiplier comprising dadda and Wallace tree multiplier uses less number of majority gates and inverters and hence minimizes area, cell count and delay. It has been observed that the QCA cost function of the proposed multiplier better than existing multiplier referred in the literature in terms of energy and speed. Furthermore, the proposed multiplier significantly achieves high device density, lessened clock delay, area and cell count and also to eliminate fabrication difficulty of crossover.

Design of Nanotechnology Based Hazard Free Digital Circuit using Quantum Dot Cellular Automata

Currently digital circuits have a high flying role in most communications applications. In this Paper, a successful approach to risk-free circuit analysis and design using quantum dot cellular automata is explored at the Nano level. This paper, which we use for both integrated and continuous digital circuits, is a basic component of QCA circuit operation. The Quantum Dot Cellular Automata Designer Tool is very useful for designing a large risk-free circuit. So the proposed risk-free circuit is designed and simulated using this designing software utensil for three input stages. The proposed framework for the risk-free circuit requires only a small number of major gate operations compared to previous structures because of its three input levels.

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACTEnergy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology

This paper focuses on a novel design of an adder/subtractor-based incrementer/decrementer using quantum-dot cellular automata (QCA) technology. QCA is a promising nanotechnology that offers new techniques of computation and data transmission. We use the multilayer crossover technique in the proposed designs to achieve low latency and area for the scalability feature. Moreover, new designs of QCA half and full adders are proposed to improve the operating speed of the incrementer/decrementer. The working of the proposed designs is analyzed via the QCA simulator tool, and the results are compared with previous studies in terms of cell count, area, and latency. According to the analysis, the presented designs perform well; for example, the proposed 4-bit incrementer design shows an improvement of 65 % in terms of area usage and 3.2 times lower latency compared to its existing counterpart.

A combined three and five inputs majority gate-based high performance coplanar full adder in quantum-dot cellular automata

Nowadays, arithmetic computing is an important subject in computer architectures in which the one-bit full-adder gate plays a significant role. Thus, efficient design of such full-adder component can be beneficial to the overall efficiency of the entire system. In this essay, a novel method for the design and simulation of a combined majority gate toward realization of the one-bit full-adder gate is proposed. We inspect an alternative approach for the streamlined physical design of quantum-dot cellular automata (QCA) full-adder circuits in which the placement of input cells and wire crossing congestion are substantially reduced. The proposed method has outstanding characteristics such as low complexity, reduced area consumption, simplified physical design, and ultra-high speed one-bit full-adder. Based on simulation results the proposed design provides 33.33% reduction in area and 20.00% improvement in complexity as well as 10.49% in 1 Ek reduction in power consumption.

Design and simulation of nano-arbiters using quantum-dot cellular automata

Arbiters are the essential components of the Network-On-Chip (NOC) systems and are used to resolve the contention problem where multiple requests must be handled for shared resources. On the other hand, with the ever-increasing downsizing trend in the fabrication technology, Quantum-dot Cellular Automata (QCA) with its nano scales and very low power consumption is a promising candidate for implementing future NOCs. In the current work, we design and simulate nano-arbiters using QCA with the following contributions: i) The 2-bit Basic Round Robin Arbiter (RRA) and the 2-bit Ping Pong Arbiter (PPA) are designed and simulated; ii) A solution for an erroneous condition found in the original circuit of RRA is reported and fixed; iii) We use Cartesian Genetic Programming (CGP) approach to simplify the RRA and PPA designs; iv) In order to leverage our QCA designs, we apply a more realistic clock distribution (2-DW clocking) and report the results. At the end, a one-to-one comparison of the two arbiters designed with QCA will be presented using such benchmarks as area, latency, etc. Our results show that in the 2-bit input mode, the PPA arbiter has the best overall performance.

A Novel QCA based Compact Scan Flip-flop for Digital Design Testing

Quantum-dot Cellular Automata (QCA) is an emerging technology used for computation at nano scale. It is an excellent alternative for the conventional CMOS technology. QCA provides us with low energy, high speed, faster switching speed and compact structures for logical circuits. Testing is the integral part of the design verification, scan flip-flop is used for device testing. It is used in processors for a built-in self-test. The objective of this paper is to design an optimized structure of a scan flip-flop which occupies less area and dissipates minimum energy compared to the previously designed architectures. The efficiency of the proposed structure is analyzed in terms of cell count, energy dissipation, and area occupied by the logical circuit. Proposed scan flip flop has a cell count of 32 and an energy dissipation of 0.0105 eV which is 20 % more efficient in terms of cell count and 29 % more efficient than the previous designs. The CAD tool, QCA Designer is used for design and simulation. Cells have a dimension of 18 nm in height and 18 nm in breadth and there is a distance of 2 nm between these cells. Bi-stable and coherence vector simulation engines are used in the tool for simulation.

New Design of a 4-Bit Ripple Carry Adder on a Nano-Scale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is a new computing paradigm based on cellular automata with appealing characteristics such as high speed, low power consumption, and high density for realizing quantum computers. On the other hand, an adder is the primary circuit in any digital processor and ripple carry adder is a basic building block of other adders. Therefore, efficient design of this type of adder may lead to the efficient design of the whole system. So, in this paper, a new design of ripple carry adder is proposed to decrease the number of cells and area as possible. Simulation results using QCA Designer verifies the correctness of the proposed circuit and validates its efficiency in terms of a number of cells and area.

Designing majority gate-based nanoscale two-dimensional two-dot one-electron parity generator and checker for nano-communication

At the present time, logic circuits design prototypes with quantum-dot cellular automata (QCA) have been comprehensively researched. The confines of orthodox CMOS technology induce to the breakthroughs of different technologies, one of which is QCA. Thoughtlessly, because of the deficiency of advance assembly support, QCA circuits frequently agonize from several sorts of manufacture shortcomings and variations and, hence, are error prone and defective. QCA technology is forming its aspect due to extreme effectiveness and rapidity with lesser area requirement. This study, a novel architecture of parity generator and checker, is proposed based on two-dot one-electron cells. Parity generator and checker assist in impeccable binary information communication from point to point. With the outlined parity generator and checker circuit, a nano-communication architecture is designed. The designed architecture is rationalized with a competently established standard mathematical operation based on Coulomb’s theory. All the outlined design contains a minimum number of cells, extent, and energy compared to existing four-dot two-electron QCA designs. The outlined designs comprehend minimum majority gate and latency. Besides, power depletion by the designs is measured and it is perceived that the total energy and power required to operate these designs are incredibly low.

Next Generation Computing Using Quantum Dot Cellular Automata Nano Technology, New Promising Alternative to CMOS

CMOS technology is one of the most popular technology in the computer chip design industry and broadly used today to form integrated circuits in numerous and varied applications and it has transformed the field of electronics. Over the time the design methodologies and processing technologies of CMOS devices have greatest activity with the Moore’s law. Now CMOS technology has to face challenges to survive through the submicron ranges. The scaling in CMOS has reached higher limit, not only from technological and Physical point of view but also from economical and material aspects. This concept inspires the researches to look for new alternatives to CMOS which gives better performance and power consumption. One of the alternative technologies to digital designing in CMOS is the Quantum dot Cellular Automata (QCA). QCA is a technology it works on Electronic interaction between the cells. The QCA cell basically consists of Quantum dots separated by certain distance. The transmission of information done via the interaction between the Electrons present in these quantum dots. In this paper the limitations to CMOS in submicron range and concepts for designing in QCA have been discussed and also the building blocks are explained using QCA designer implementations with focus on cell interaction and clocking mechanism.

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates

Quantum-dot cellular automata (QCA) is one of the promising technologies that enable nanoscale circuit design with high performance and low-power consumption features. As memory cell and flip-flops are rudimentary for most of the digital circuits, having a high speed, and a less complex memory cell is significantly important. This paper presents novel architecture of D flip-flops and memory cell using a recently proposed five-input majority gate in QCA technology and simulated by QCADesigner tool version 2.0.3. The simulation results show that the proposed D flip-flops and the memory cell are more superior to the existing designs by considering the common design parameters. The proposed RAM cell spreads over an area of 0.12[Formula: see text][Formula: see text]m2and delay of 1.5 clock cycles. The proposed level-triggered, positive/negative edge-triggered, and dual edge-triggered D flip-flop uses 14%, 33%, and 21% less area, whereas the latency is 40%, 27%, and 25% less when compared to the previous best design. In addition, all the proposed designs are implemented in a single layer QCA and do not require any single or multilayer wire crossing.

Quantum-Dot Cellular Automata Technology for High-Speed High-Data-Rate Networks

In today’s technology, optical networking plays a vital role in reducing data losses, thereby providing higher data rates between the transreceivers. The very large scale integration circuits in the modulator–demodulator (MODEM) usually fabricated using complementary metal oxide semiconductor (CMOS) technology have serious scaling limitations; hence, device scaling beyond 65 nm technology becomes highly challenging. Quantum-dot cellular automata (QCA) is one of the most promising nanotechnologies that enable areas of smaller size, i.e. 60% less design area than the CMOS technology, with capability to produce high speed by taking less cycles compared with the other CMOS designs to reduce scaling issues. The QCA-based designs are considered as the best alternative solutions to the transistor-based (CMOS) designs. This paper deals with the implementation of the logic gates NOT, AND, OR, NAND, NOR, XOR and XNOR using both CMOS and QCA technologies, while the QCA allows more possible design structures for each logic gate to enable optimization of the area. Finally, the proposed QCA-based logic gate design and CMOS-based designs are compared in terms of the design area, cell count and the speed of the designs. QCA designer 2.0.3 and virtuoso CADENCE Computer-Aided Design tools are used for carrying out the work.

New efficient designs of reversible logic gates and circuits in the QCA technology

Quantum-dot cellular automata (QCA) is a developing nanotechnology, which seems to be a good candidate to replace the conventional complementary metal-oxide-semiconductor (CMOS) technology. The QCA has the advantages of very low power dissipation, faster switching speed, and extremely low circuit area, which can be used in designing nanoscale reversible circuits. In this paper, the new efficient QCA implementations of the basic reversible Gates such as: CNOT, Toffoli, Feynman, Double Feynman, Fredkin, Peres, MCL, and R Gates are presented based on the straight interactions between the QCA cells. Also, the designs of 4-Bit reversible parity checker and 3-bit reversible binary to Grey converter are introduced using these optimized reversible Gates. The proposed layouts are designed and simulated using QCADesigner software. In comparison with previous QCA designs, the proposed layouts are implemented with the minimum area, minimum number of cells, and minimum delay without any wire-crossing techniques. Also, in comparison with the CMOS technology, the proposed layouts are more efficient in terms of the area and power. Therefore, our designs can be used to realize quantum computation in ultralow power computer communication.

Ultra-efficient convolution encoder design in quantum-dot cellular automata with power dissipation analysis

Nowadays, Quantum-dot Cellular Automata (QCA) is a well-known technology for designing digital systems. Actually, QCA is the most possible alternative for semiconductor transistor based technology. In this paper, an improved design of QCA based convolution encoder has been proposed. The proposed encoder outperforms previous QCA based design from the view of size, speed, and power consumption. A popular simulator, QCADesigner has been used for simulating and verifying the proposed encoder. Simulation result shows proposed encoder’s dominance against previous designs from the context of cell number, area, latency, and energy consumption. The proposed 1/2 rate and 1/3 rate encoder reveal 89% and 85% less energy consumption at 0.5Ek tunneling energy level as compared to the previous design. It is worth mentioning that 90% and 86% optimizations in the number of cells in addition to 95% and 96% optimizations in the area are achieved for the proposed 1/2 rate and 1/3 rate convolution encoder, respectively, in comparison with the previous design.

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

New designs of fault-tolerant adders in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has attracted attention as one of the best forms of alternative Nanoscale CMOS technology. It has facilitated the designing of digital circuits with high density and speed. One of the important issues in QCA technology is designing fault-tolerant digital circuits. QCA-based circuits frequently suffer from fabrication and unstable faults: these make them unreliable and susceptible to breakdown. In this paper, two new fault-tolerant 3-input majority gates have been proposed in QCA technology. The robustness of the proposed structures has been evaluated in terms of defects such as cell omission, deposition of extra cell and cell displacement defects. The simulations were performed using the QCA Designer 2.0.03 and QCAPro tools to measure performance and energy consumption. The obtained results indicate that the proposed structures benefit from higher fault-tolerant in comparison to previous designs. Moreover, we provided four new fault-tolerant full-adders and a multi-bit adder using the proposed structures and acceptable results are archived.