Design Of Low Noise Amplifier Research Articles

A novel programmable gain control low noise amplifier (PGCLNA) design for automatic gain control loop in BLE applications

Abstract Bluetooth low energy (BLE) is a widely used short-range communication protocol and BLE receivers frequently encounter transient high-power RF (radio frequency) signals from antennas, leading to receiver saturation. To address this issue, this work proposes a 2.4 GHz programmable gain control low-noise amplifier (PGCLNA), which is a key element in an automatic gain control (AGC) system for BLE receiver applications. The proposed PGCLNA achieves discrete levels of gain using the gm-boosting technique by splitting the negative feedback. The proposed circuit is simulated in UMC 180nm technology and the maximum gain achieved is 41.4 dB, with a step decrease of 15 dB in discrete levels. The gain variations do not degrade the performance of S11, which is always less than -16 dB. The noise figure (NF) is always minimum of 5.5 dB and in high gain mode, the minimum value of NF is 1.82 dB. The third-order intercept point (IIP3) is -7.621 dBm in the best circumstances and always remains above -10.69 dBm. These results are achieved by utilising 5.4 mW power at 1.8 V of supply voltage. The circuit occupies an area of 732μm × 771μm. The proposed PGCLNA design offers a solution to accommodate a wide range of input signals in BLE receivers, excellent gain control, low noise and robust performance characteristics, making it an essential component in an AGC system for BLE receiver applications.

A wideband inductorless LNA exploiting three-stage feedback and thermal noise canceling

In inductorless wideband low-noise amplifier (LNA) design, input-matching is traded off with noise figure (NF). The common-source noise-canceling (CSNC) structure and the gyrator alleviate this trade-off, but the corresponding study is insufficient. This work combines the CSNC and gyrator and introduces a three-stage feedback loop to achieve high feedback gain while minimizing the added input capacitance. Hence, the trade-off between NF and input impedance matching is significantly released. Consequently, the lowest NF among inductorless LNAs was achieved, while an operation bandwidth of more than 3 GHz was obtained. Post-layout simulation results in 40 nm CMOS technology show that the circuit achieves an NF of 1.35 dB–1.7 dB while maintaining a wide operation bandwidth of 100 MHz to 3.46 GHz. As far as the author knows, this is the lowest NF inductorless LNAs have achieved. Furthermore, S21 of 10.9 dB and IIP3 (input third-order intercept point) of −5.6 dB m are obtained, and the circuit consumes 14.9 mW at a 1.2 V voltage supply. Being self-biased, the circuit core consumes only 0.0032 mm2 die area.

A gyrator-C active inductor based tunable low noise amplifier for sub-GHz frequency range

The propose exhibits a tunable low noise amplifier (LNA), which provides the tunability at sub-GHz frequency range and hence can become choicest frequency range for 5 G applications. Common source (CS) with source degeneration inductor LNA is proposed; in which the inductor in source branch is replaced by gyrator-c active inductor which not only reduced the overall area of the circuit but can also be used to provide the feature of tunability by changing the bias voltage of CMOS based active resistor in feedback branch. Therefore, instead of having a LNA circuit for the fixed frequency, a single tunable LNA design can be used over a range of frequency from 1 GHz to 5 GHz. The proposed approach will provide the direct tuning to the circuit. The forward voltage gain achieved is greater than 10 dB, input matching parameter is less than −10 dB and the output matching parameter is less than −10 dB. The average power dissipated is 0.02 W. The results can be tuned by controlling the feedback voltage of tunable active inductor (Tunable_AI). The tunable results can be achieved up to the bandwidth of 1 GHz.

Blocker tolerant cascode LNA for Wifi & IoT applications

SummaryWithin the domain of contemporary wireless communication systems, crafting Low‐Noise Amplifiers (LNA) holds a pivotal significance in achieving heightened signal sensitivity and comprehensive system efficacy and suppresses noise contributions from subsequent stages. Additionally, the low noise figure (NF) and high gain are critical LNA performance parameters in portable applications. Normally, LNA contains issues in noise performance, amplification, bandwidth, gain, and stability. To overcome these challenges, there must be a proper selection of transistors, harmonious impedance calibration, bias optimization, and circuit fine‐tuning. Moreover, metal oxide semiconductor field effect transistors (MOSFETs) are a popular choice in LNA design because of their excellent noise performance, high input impedance, complementary metal‐oxide semiconductor (CMOS) integration capabilities, low power operation, and suitability for a wide range of frequency applications. Through simulation and iterative enhancement, the LNA showcases remarkable Noise Figure, amplification, and linearity over a designated frequency span. This creation contributes to the advancement of radio frequency (RF) circuitry by designing an approach for LNA crafting that harmonizes conflicting prerequisites and unveils effective noise mitigation tactics. The outcomes emphasize the importance of a deliberated circuit architecture and parameter adjustment in accomplishing superlative LNA capabilities, rendering it fit for assimilation into diverse communication systems that demand minimal noise and heightened sensitivity.

A 3.2-3.8 GHz low-noise amplifier for 5G/6G satellite-cellular convergence applications

The rapid evolution of wireless communication systems towards 5G standards has imposed stringent requirements on the performance of radio frequency front-end components. Among these, the Low-Noise Amplifier (LNA) plays a pivotal role in determining the overall noise figure and sensitivity of the receiver chain. This paper presents a comprehensive design and analysis of a 3.2-3.8 GHz LNA tailored for 5G applications, employing a 0.3 μmm gate length Gallium Arsenide (GaAs) pseudomorphic high electron transistor (pHEMT) technology process. The proposed LNA design focuses on achieving a low noise figure (NF), high gain, and robust linearity to accommodate the dense signal environment and wide bandwidth of 5G networks. The design leverages advanced matching networks and feedback topologies to enhance stability and reduce the noise contribution from the active devices. Simulation results predict a noise figure of 1.3-1.4 dB, a gain of 20-21 dB across the band of interest, and an input-referred third-order intercept point (IIP3) of 18 dBm. The LNA demonstrates excellent performance in a 5G testbed, showing a significant improvement in the signal-to-noise ratio and the potential to enhance 5G receiver sensitivity. The research substantiates the LNA’s viability for integration into 5G base stations and user equipment, underscoring its potential to contribute to the efficient and reliable operation of next-generation wireless networks. This LNA can be used for 5G New Release (NR) band of n77 and n78 (3.5-3.7 GHz)

A gm/ID-Based Low-Power LNA for Ka-Band Applications.

This article presents the design of a low-power low noise amplifier (LNA) implemented in 45 nm silicon-on-insulator (SOI) technology using the gm/ID methodology. The Ka-band LNA achieves a very low power consumption of only 1.98 mW andis the first time the gm/ID approach is applied at such a high frequency. The circuit is suitable for Ka-band applications with a central frequency of 28 GHz, as the circuit is intended to operate in the n257 frequency band defined by the 3GPP 5G new radio (NR) specification. The proposed cascode LNA uses the gm/ID methodology in an RF/MW scenario to exploit the advantages of moderate inversion region operation. The circuit occupies a total area of 1.23 mm2 excluding pads and draws 1.98 mW from a DC supply of 0.9 V. Post-layout simulation results reveal a total gain of 11.4 dB, a noise figure (NF) of 3.8 dB, and an input return loss (IRL) better than 12 dB. Compared to conventional circuits, this design obtains a remarkable figure of merit (FoM) as the LNA reports a gain and NF in line with other approaches with very low power consumption.

Design of Multiple Feedback-Based Low-Noise Amplifier With Improved Broadband Simultaneous Noise and Impedance Matching Technique

Design of Multiple Feedback-Based Low-Noise Amplifier With Improved Broadband Simultaneous Noise and Impedance Matching Technique

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

Design of a Low Power Low-Noise Amplifier with Improved Gain/Noise Ratio

Low noise amplifier design for hidden wireless lan applications using band pass filter with geometric mean prototype element values

Low noise amplifier design for hidden wireless lan applications using band pass filter with geometric mean prototype element values

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

Analysis of Indirect Lightning Effects on Low-Noise Amplifier and Protection Design

In order to analyze the interference mechanisms of indirect lightning effects on a low-noise amplifier (LNA), a circuit model of the LNA was constructed based on the advanced design system 2020 (ADS 2020) software. Lightning pulse injection simulations were conducted to explore the influence of lightning pulses on the performance of the LNA. A pin injection test was performed to investigate the interference and damage threshold of the LNA. A protective circuit incorporating the transient voltage suppressor (TVS) and Darlington structure was designed through simulation, employing the ADS 2020 for the LNA. The research findings reveal that the interference threshold for the LNA is 60 V, while the damage threshold is determined to be 100 V. The protective circuit demonstrates a measured insertion loss of 0.1 dB, a response time of 1.5 ns, and a peak output voltage of 20 V. The research results indicate that the protective circuit can effectively reduce the impact of lightning’s indirect effects on the LNA. In the future, we will continue the design work of the protective circuit and proceed with physical fabrication and experimental validation.

High-Efficiency Low Noise Amplifier Design for Enhanced Receiver Sensitivity in S- and C- band Frequencies

High-Efficiency Low Noise Amplifier Design for Enhanced Receiver Sensitivity in S- and C- band Frequencies

A Low Noise Amplifier with 27 dB Gain and 1.78 dB Noise for Satellite Communications with 0.1 µm GaAs pHEMT Technology

This paper proposes a design of a 38 GHz Low Noise Amplifier (LNA) that uses a three-stage common source inductive degeneration topology with a gain of 27 dB and noise figure of 1.78 dB using 0.1 µm GaAs pHEMT as an active device. The novelty of the design is the usage of inductive load in series with the resistor instead of resistive load, resulting in higher gain performance. A recent pp1010 active device of WIN foundry was explored for this LNA design at the Q band. The high transition frequency offered by this technology succeeded in obtaining competitive results with a minimum number of cells. The designed LNA obtained the lowest noise compared to other recently published LNA designs at the Q band. The total power consumption of this design is 57 mW.

Current Re-Use Architecture and Pre-Distortion Technique Employing Re-Configurable Low Noise Amplifier for the Design of Nano-Electronic Sensors

This study presents the design of reconfigurable CMOS Low Noise Amplifier (LNA) topologies to achieve acceptable linearity, gain, and low noise for Nano-sensor applications. The frequency bands at 2.4 GHz, 5 GHz and 28 GHz are taken into consideration for employing the Pre-distortion and current reuse technique. Millimeter Wave (MMW) frequency bands include excellent impedance matching, good isolation between the ports, To improve the futuristic applications of RADAR sensors, low noise figures and significant gain are preferred. The designed re-configurable structure achieved At 2.4 GHz, the gain is modest with a low NF of 2.6 dB, less than 2 dB at 5 GHz, and more than 10 dB at 28 GHz frequencies. The Stability of the amplifier greater than 1 dB, The arrangement of the layout with a chip measuring 0.5×0.2 mm2 and a moderate power increase make it appropriate for nanosensor creation.

Multi-objective optimization of CMOS low noise amplifier through nature-inspired swarm intelligence

This paper presents the application of two swarm intelligence techniques, multi-objective artificial bee colony (MOABC) and multi-objective particle swarm optimization (MOPSO), to the optimal design of a complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) cascode with inductive source degeneration. The aim is to achieve a balanced trade-off between voltage gain and noise figure. The optimized LNA circuit operates at 2.4 GHz with a 1.8 V power supply and is implemented in a 180 nm CMOS process. Both optimization algorithms were implemented in MATLAB and evaluated using the ZDT1, ZDT2, and ZDT3 test functions. The optimized designs were then simulated using the advance design system (ADS) simulator. The results showed that the MOABC and MOPSO techniques are practical and effective in optimizing LNA design, resulting in better performance than previously published works, with a gain of 21.2 dB and a noise figure of 0.848 dB.

DESIGN OPTIMIZATION OF LOW NOISE AMPLIFIER FOR 900MHZ GSM BAND APPLICATIONS USING GREY WOLF ALGORITHM

In this work, the design of a high-performance single-stage Low Noise Amplifier (LNA) for GSM applications is taken into consideration. LNA design is one of the key stages of a wireless communication system due to its dominance over the whole system's noise figure performance. Although it is possible to achieve a very high gain and low noise figure with the usage of multi-stage transistors, such designs would also have a high complexity and manufacturing cost. The main aim of this work is to propose a single transistor LNA design for GSM application with a gain level of 14.3 dB, return loss level of less than 15 dB, and noise figure of 1.8 dB over the operation band of 820-980 MHz. the optimal design variables of the model is obtained via Grey Wolf optimization procedure.

Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors

This paper proposes the technique of using low loss on-chip inductors in the design of low noise amplifier (LNA) that offers high gain and lower noise figure. Upon the substrate of octagonal spiral inductors, a surface of patterned ground shield is inserted that significantly reduces the substrate loss. This effect limits the penetration of electric filed into the substrate, thereby improving the inductor’s Quality (Q) factor and decouples the substrate parasitic that results with smaller series resistance. These effects result with improved gain and noise figure of LNA at 60 GHz when the designed inductors are included in it to serve as gate, source, and load inductances. The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. The figure-of-merit (FOM) is 14.56 which is 0.8 times more than the LNA design using off-chip inductors. A complete LNA layout using custom designed inductor footprints has been presented and analyzed.

Wideband SiGe-HBT Low-Noise Amplifier with Resistive Feedback and Shunt Peaking.

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage-current (shunt-shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit's core active elements in the main branch. The measurement results show an operational bandwidth of 2.0-29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of -5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs.

A compact 9–23 GHz low noise amplifier with bandwidth extension techniques in 0.18‐μm SiGe BiCMOS

AbstractIn this paper, a novel wideband low noise amplifier (LNA) operating in the 9–23 GHz frequency range is presented. The proposed LNA design utilizes a combination technique consisting of pole‐tuning technique, shunt resistive‐capacitor negative feedback, and gate‐capacitive peaking technique to achieve significant bandwidth extension while maintaining acceptable overall performance. For verification, a one‐stage triple‐stacked LNA using the combination technique is designed and implemented in a 0.18‐μm SiGe BiCMOS heterojunction bipolar transistor (HBT) process. The fabricated prototype demonstrates a peak gain of 13.8 dB at 19.5 GHz, minimum noise figure of 3.1 dB at 14 GHz, 3‐dB bandwidth of 14 GHz, and a fractional bandwidth of 87.5%, while consuming a dc power of 39.6 mW. Moreover, the chip occupies a small silicon area of 0.39 mm2 including all testing pads with a core size of only 0.192 mm2.

Mutually coupled CG-CS current reuse low noise amplifier architecture for 4 – 14 GHz frequency

Abstract The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34.