Design Of Low-dropout Regulator Research Articles

Low power consumption and fast response of low dropout regulator design

A low power consumption and fast response low voltage difference linear regulator circuit is designed for on-chip SOC circuit to achieve low power consumption, fast response, and high stability. The internal design mainly includes a low power bandgap reference circuit, a light and heavy load detection circuit, and a transient enhancement circuit. The circuit is designed with 0.35 μm BCD technology, and the layout design is completed. The VIN is from 2.5 V to 5 V, the VOUT from 2.5 V to 3.3 V, and the maximum load is 250 mA. The simulation results show that the static current is 2.6 μA at normal temperature with no load. When the load jumps, the overshoot is 44 mV and the recovery time is 52 μs, meeting the design requirements of low power consumption and fast response.

Three-Stage CMOS LDO with Optimized Power and Dynamic Performance for Portable Devices

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power (Iq = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications.

Bandgap reference, temperature sensor and low drop-out regulator circuits monolithic sensors in TPSCo 65 nm ISC technology

With Inner Tracking System v3 (ITS3), the ALICE experiment is pursuing a wafer-scale Monolithic Active Pixel Sensor (MAPS). The chip is being developed in TPSCo 65 nm ISC technology which is under study in the framework of CERN EP R&D on monolithic sensors for High Energy Physics (HEP) applications. This contribution presents designs and measurement results of building blocks needed for this chip, in particular bandgap references and temperature sensors. In addition, simulation results of the design of Low Drop-out Regulator (LDO) to be submitted for the next prototyping run will be discussed.

Design of Capacitor-less LDO applied to Low Power Supply with High-precision Bandgap

This paper proposes a capacitor-less low dropout regulator (LDO) applied to low power supply to meet the needs of low power consumption and highly integration. In order to improve the transient response of the system, a dynamic bias circuit is designed, which can automatically track the change of load current. In addition, the temperature coefficient of bandgap reference in conventional LDO is generally 20-100 ppm/°C. The bandgap reference circuit proposed in this paper can achieve 1.73 ppm/°C without trimming, and the accuracy is better than 1% at all process corner. The design and simulation are based on TSMC 0.18 μm CMOS process, the simulation results show that the LDO output voltage is 1 V when input power supply voltage is 1.2 V. The proposed regulator can operate with a minimum dropout voltage of 200 mV when load current is 50 mA. The maximum undershoot and overshoot voltages are 34 mV and 28 mV, respectively, with 1mA-50mA and 50mA-1mA step load current.

Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design

Using coaxial through-silicon technologies, a new 3-D capacitor integrated on a silicon interposer is proposed. The capacitance of coaxial through silicon via (CTSV) capacitors is extracted, analyzed, and compared. The results obtained from the analytical model and the finite-element method exhibit good agreement with various design parameters, and the error between the proposed model and measurement remains less than 7.41%. Due to high capacitance density up to 22.4 nF/mm2, the 3-D capacitor is adopted as a decoupling capacitor for the on-chip low-dropout (LDO) regulator design. The proposed LDO is developed in a 180-nm CMOS technology and shows unique advantages regarding the power supply rejection (PSR) performance, quiescent current, and area compared with that of the conventional LDOs with off-chip capacitors and capacitor-less (CL) LDOs.

A Design of Low-dropout Regulator with Adaptive Threshold Voltage Technique

In this paper, the characteristics of Low Dropout Regulators to which the adaptive threshold voltage technique was applied were analyzed. For this analysis, fore types of LDO were fabricated. Also Proposed LDO is fabricated in 0.18 um BCD process. The first was a conventional LDO. For the second type of LDO, the adaptive threshold voltage technique was applied to the error AMP and voltage buffer; for the third type of LDO, the adaptive threshold voltage technique was applied to the pass TR and for the fourth type of LDO, the adaptive threshold voltage technique was applied to the error AMP, voltage buffer, and pass TR. The adaptive threshold voltage technique applies a separate voltage to the body terminal of transistor to reduce the threshold voltage (Vth) and increase the drain current. In this paper, the adaptive threshold voltage technique was applied to each block. Then the characteristics and areas of the four types were comparatively analyzed. The area of the current-mirror of the error AMP and voltage buffer proposed in this paper decreased by about 61% compared to the conventional current-mirror. Furthermore, the area of the pass TR proposed in this paper decreased by 5.5% compared to the conventional pass TR and the regulation characteristic of the LDO improved

PSR enhancement techniques for output-capacitor-free LDO regulator design

In this paper, power-supply rejection (PSR) enhancement techniques for a output-capacitor-free low drop-out (LDO) regulator with an NMOS pass transistor are presented. For DC PSR and bandwidth enhancement, DC PSR compensation and capacitor cancelation circuits were developed on the basis of precisely derived PSR models of the conventional LDO regulator. The effectiveness of the PSR enhancement techniques were verified using analytic PSR models, SPICE simulation, and measurements. The fabricated LDO regulator using 0.18 \(\upmu\)m CMOS technology maintains PSR less than \(-74\,\hbox {dB}\) up to 10 MHz, while delivering the output current and voltage of 25 mA and 1.2 V, respectively.

DESIGN OF CMOS LOW DROP-OUT REGULATORS: A COMPARATIVE STUDY

The advancement in battery operated portable devices, noise sensitive devices and other devices, which need high precision supply voltages has fuelled the growth of Low Drop-Out Regulators. Low Drop-Out Regulators showed advantage over its counterpart. The design of Low Drop-Out Regulators with high performance and less Die area is challenging problem now-a-days. This paper is a study of various techniques that are used to achieve better performance of low drop-out regulators.Â

A wireless and batteryless microsystem with implantable grid electrode/3-dimensional probe array for ECoG and extracellular neural recording in rats.

This paper presents the design and implementation of an integrated wireless microsystem platform that provides the possibility to support versatile implantable neural sensing devices in free laboratory rats. Inductive coupled coils with low dropout regulator design allows true long-term recording without limitation of battery capacity. A 16-channel analog front end chip located on the headstage is designed for high channel account neural signal conditioning with low current consumption and noise. Two types of implantable electrodes including grid electrode and 3D probe array are also presented for brain surface recording and 3D biopotential acquisition in the implanted target volume of tissue. The overall system consumes less than 20 mA with small form factor, 3.9 × 3.9 cm2 mainboard and 1.8 × 3.4 cm2 headstage, is packaged into a backpack for rats. Practical in vivo recordings including auditory response, brain resection tissue and PZT-induced seizures recording demonstrate the correct function of the proposed microsystem. Presented achievements addressed the aforementioned properties by combining MEMS neural sensors, low-power circuit designs and commercial chips into system-level integration.

A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator

In this paper, a low power current protection circuit implemented in a low dropout regulator (LDO) is presented. The proposed circuit, designed in a 0.35 μm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed that the proposed circuit is operable in the regulator output voltage range from VOUT=1.2V to VOUT=3.6V and supply voltage range from VDD=VOUT+0.5 V to VDD=5.6 V. Since the proposed circuit is composed of few simple basic circuits such as a comparator and a Schmitt Trigger, it has a low current consumption of less than IS S=0.82 μA at a load current of ILOAD=200 mA. This makes the circuit suitable for low power and low voltage LDO design.

Low-cost area-efficient low-dropout regulators using MOSFET capacitors

Traditional design of low-dropout regulators offers the use of metal-insulator-metal (MIM) compensation capacitors to avoid instability in the absence of output capacitance with equivalent series resistance (ESR). In addition to area efficiency achieved by replacing these capacitors with MOS transistors, the location of implanted transfer function poles and zeros are adaptively varied according to the value of load current. This idea has been applied to stabilize a 1.2V, 100mA low-dropout regulator in an industrial 0.18µm CMOS n-well process. Using the proposed technique, the regulator meets stability with a small 100pF MOSFET output capacitor and no ESR.